专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010053756A2 METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY 审中-公开
标题翻译：改进串口存储器通信延迟和可靠性的方法和系统
公开(公告)号：WO2010053756A2
公开(公告)日：2010-05-14
申请号：PCT/US2009/062231
申请日：2009-10-27
申请人： SILICON IMAGE, INC. , RUBERG, Alan , LEE, Seung-jong , LEE, Hyung, Rok , SHIM, Daeyun , LEE, Dongyun , KIM, Sungjoon , MURTHY, Anu
发明人： RUBERG, Alan , LEE, Seung-jong , LEE, Hyung, Rok , SHIM, Daeyun , LEE, Dongyun , KIM, Sungjoon , MURTHY, Anu
IPC分类号： G06F13/42
CPC分类号： G11C7/1075 , G06F11/141 , G06F11/1443 , G06F13/1663 , G06F13/4234 , G11C5/066 , Y02D10/14 , Y02D10/151
摘要： A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
摘要翻译：公开了一种用于减少存储器延迟的方法，装置和系统。在一个实施例中，主计算机系统和存储器之间的数据经由多个时间间隔上的存储器端口或一组端口进行通信，其中主计算机耦合到存储器。此外，与数据相关联的命令在主计算机系统和存储器之间通过端口或端口组通过单个时间间隔进行通信。

2. 发明申请

WO2007115226A2 INTER-PORT COMMUNICATION IN A MULTI- PORT MEMORY DEVICE 审中-公开
标题翻译：多端口存储器中的端口间通信
公开(公告)号：WO2007115226A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/065722
申请日：2007-03-30
申请人： SILICON IMAGE, INC. , RUBERG, Alan , KIM, Dae, K. , SHIM, Daeyun , LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
发明人： RUBERG, Alan , KIM, Dae, K. , SHIM, Daeyun , LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.
摘要翻译：一种利用多端口存储器件进行端口间通信的方法和系统。存储器件包含中断寄存器，中断信号接口（例如，专用引脚），中断掩码以及与每个端口相关联的一个或多个消息缓冲器。当耦合到存储设备的第一端口的第一组件想要与耦合到存储器设备的第二端口的第二组件通信时，第一组件将消息写入与第二端口相关联的消息缓冲器。第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。在接收到中断时，第二个组件读取中断寄存器以确定中断的性质。然后第二个组件从消息缓冲区读取消息。

3. 发明申请

WO2008118816A1 PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE 审中-公开
标题翻译：多端口存储器件的逐步功率控制
公开(公告)号：WO2008118816A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/057920
申请日：2008-03-21
申请人： SILICON IMAGE, INC. , KIM, Sungjoon , LEE, Dongyun , KIM, Edward
发明人： KIM, Sungjoon , LEE, Dongyun , KIM, Edward
IPC分类号： G11C5/14
CPC分类号： G06F1/3275 , G06F1/3225 , G11C7/1075 , G11C7/22 , Y02D10/14 , Y02D50/20
摘要： A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.
摘要翻译：提供了一种逐渐降低串行存储设备的功耗的方法和系统，称为功率控制系统。电源控制系统监视多端口串行存储器的端口，以便可以在每个端口的基础上启用或禁用它们。当在端口上没有发送或接收数据时，采取一系列步骤逐步取消对端口的部分断电，并使端口进入低功耗状态。通过禁用某些端口并将端口置于低功耗状态，整个串行端口存储器的功耗显着降低。

4. 发明申请

WO2007115229A1 SHARED NONVOLATILE MEMORY ARCHITECTURE 审中-公开
标题翻译：共享非易失性存储器架构
公开(公告)号：WO2007115229A1
公开(公告)日：2007-10-11
申请号：PCT/US2007/065727
申请日：2007-03-30
申请人： SILICON IMAGE, INC. , CHO, Myung, Rai , LEE, Dongyun , RUBERG, Alan
发明人： CHO, Myung, Rai , LEE, Dongyun , RUBERG, Alan
IPC分类号： G06F9/445
CPC分类号： G06F15/177 , G06F9/4405
摘要： A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.
摘要翻译：一种利用共享非易失性存储器来初始化设备中的多个处理组件的方法和系统。用于处理设备内的组件的启动逻辑和配置数据存储在单个非易失性存储器中。在接收到用于初始化设备的命令时，共享存储器系统将启动逻辑和配置数据从非易失性存储器复制到易失性主存储器。然后，每个处理组件访问主存储器以找到其启动逻辑和配置数据并开始执行。共享存储器系统减少用于初始化多个处理组件的非易失性存储器组件的数量。

5. 发明申请

WO2007115227A2 MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 审中-公开
标题翻译：具有可变端口速度的多端口存储器件
公开(公告)号：WO2007115227A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/065723
申请日：2007-03-30
申请人： SILICON IMAGE, INC. , LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
发明人： LEE, Dongyun , CHO, Myung, Rai , KIM, Sungjoon
IPC分类号： G11C7/10 , G11C8/16
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
摘要翻译：具有两个或多个端口的多端口存储器件，其中每个端口可以以不同的速度操作。多端口存储器件包含可通过两个或更多个端口访问的存储体。每个端口都应用两个时钟信号：系统时钟和端口时钟。系统时钟被应用于与存储体接口的端口逻辑，使得端口都以相对于存储体的公共速度运行。端口时钟应用于与每个端口相关联的时钟分频器电路。端口时钟被分为所需频率或保持在其原始频率。这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

6. 发明申请

WO2009073331A1 BANK SHARING AND REFRESH IN A SHARED MULTI-PORT MEMORY DEVICE 审中-公开
标题翻译：在共享的多端口存储器装置中的银行分享和刷新
公开(公告)号：WO2009073331A1
公开(公告)日：2009-06-11
申请号：PCT/US2008/083284
申请日：2008-11-12
申请人： SILICON IMAGE, INC. , LEE, Dongyun
发明人： LEE, Dongyun
IPC分类号： G11C7/10 , G11C8/12 , G11C8/16 , G11C11/40
CPC分类号： G11C8/16 , G11C7/1075 , G11C8/12 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C11/4087
摘要： A method and system for sharing banks (110) of memory in a multi-port (120) memory device (100) between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory.
摘要翻译：提供了一种用于在组件之间的多端口（120）存储设备（100）中共享存储器的存储器（110）的方法和系统。多端口存储器设备包括系统的组件所连接的多个端口以及由多个端口存储器设备中的每个端口共享的多组存储器。每个存储器组中的每个端口都添加了一个银行可用性引脚。当银行可用于特定端口时，银行可用性信号指示信号，当银行不可用时，银行可用性信号不被信号。因此，多端口存储设备可以由几个组件同时与少量附加硬件共享以支持共享。还提供了刷新存储器组的方法。

7. 发明申请

WO2008118821A1 POWER-SAVING CLOCKING TECHNIQUE 审中-公开
标题翻译：省电时钟技术
公开(公告)号：WO2008118821A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/057926
申请日：2008-03-21
申请人： SILICON IMAGE, INC. , LEE, Dongyun
发明人： LEE, Dongyun
IPC分类号： H03L7/06
CPC分类号： G06F1/324 , G06F1/3215 , Y02D10/126 , Y02D50/20
摘要： A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit.
摘要翻译：提供了一种称为混合时钟系统的用于提供具有降低的功耗的时钟信号的方法和系统。混合时钟系统使用PLL进行高速数据传输，但提供了一种省电模式，用于传输数据，同时消耗较少的功耗。在正常模式下，混合时钟系统包含以驱动PLL的低频工作的参考时钟。 PLL将参考时钟频率乘以高得多的频率，并将时钟信号提供给数据传输电路。在省电模式下，混合时钟系统关闭PLL并将参考时钟直接连接到数据传输电路。

8. 发明申请

WO2004023268A2 METHOD AND APPARATUS FOR DOUBLE DATA RATE SERIAL ATA PHY INTERFACE 审中-公开
标题翻译：用于双数据速率串行ATA PHY接口的方法和装置
公开(公告)号：WO2004023268A2
公开(公告)日：2004-03-18
申请号：PCT/US2003/028121
申请日：2003-09-08
申请人： SILICON IMAGE, INC.
发明人： KIM, Ook , KIM, Sungjoon , NORMAN, Robert , HO, Chi Wai , LEE, Frank , LEE, Dongyun , AHN, Gijung , HWANG, Seung Ho
IPC分类号： G06F
CPC分类号： G06F13/385 , G06F13/4022
摘要： A method for multiplexing control signals for disk drives includes developing parallel control signals and developing serial control signals. At least one of the parallel control signals and the serial control signals are coupled to at least one of a parallel hard disk drive and a serial hard disk drive by a common control bus.
摘要翻译：用于多路复用用于磁盘驱动器的控制信号的方法包括开发并行控制信号和开发串行控制信号。并行控制信号和串行控制信号中的至少一个通过公共控制总线耦合到并行硬盘驱动器和串行硬盘驱动器中的至少一个。

9. 发明申请

WO2011088153A2 VIDEO MANAGEMENT AND CONTROL IN HOME MULTIMEDIA NETWORK 审中-公开
标题翻译：家庭多媒体网络中的视频管理和控制
公开(公告)号：WO2011088153A2
公开(公告)日：2011-07-21
申请号：PCT/US2011/021030
申请日：2011-01-12
申请人： SYNERCHIP USA CORP. , LEE, Dongyun , PAK, Edward , HAHN, John , GUPTA, Mayank , HENINWOLF, Paul , KIM, Byoung, Woon , KIM, Sangwan , CHO, Sukjae
发明人： LEE, Dongyun , PAK, Edward , HAHN, John , GUPTA, Mayank , HENINWOLF, Paul , KIM, Byoung, Woon , KIM, Sangwan , CHO, Sukjae
CPC分类号： H04N21/43615 , G06F13/4286 , G09G2370/047 , G09G2370/12 , H04L12/2838 , H04L2012/2849 , H04N21/43632 , H04N21/43635 , H04N21/63
摘要： A system may include a video link and a hybrid link that connects a transmitting device to the receiving device, and at least one intermediate hop between the transmitting device and the receiving device. The intermediate hop may be configured to relay video content from the video source to the video sink through the hybrid link using one or more data relay modes. The hybrid link may be configured to perform hybrid link control signaling (HLCS) to manage a physical layer of the hybrid link. The video link between the video source and the video sink may be configured to transmit a video stream the from video source to the video sink over one or more video lanes. A video link training may be implemented for the video link and the hybrid link.
摘要翻译：系统可以包括将发射设备连接到接收设备的视频链路和混合链路，以及发射设备和接收设备之间的至少一个中间跳跃。中间跳可被配置为使用一个或多个数据中继模式通过混合链路将视频内容从视频源中继到视频宿。混合链路可以被配置为执行混合链路控制信令（HLCS）以管理混合链路的物理层。视频源和视频接收器之间的视频链接可以被配置为通过一个或多个视频通道将来自视频源的视频流传输到视频接收器。视频链接训练可以针对视频链接和混合链接实施。

10. 发明申请

WO2011006146A9 SUBSTANTIALLY RIGID COLLAPSIBLE LINER AND FLEXIBLE GUSSETED OR NON-GUSSETED LINERS AND METHODS OF MANUFACTURING THE SAME AND METHODS FOR LIMITING CHOKE-OFF IN LINERS 审中-公开
公开(公告)号：WO2011006146A9
公开(公告)日：2011-01-13
申请号：PCT/US2010/041629
申请日：2010-07-09
申请人： ADVANCED TECHNOLOGY MATERIALS, INC. , TOM, Glenn , BAUM, Tom , KUSZ, Matt , MENNING, Joseph , NELSON, Greg , LEE, Dongyun , LIU, Wei , KIM, Kanghyun , BOGGS, Karl , CHISM, Richard
发明人： TOM, Glenn , BAUM, Tom , KUSZ, Matt , MENNING, Joseph , NELSON, Greg , LEE, Dongyun , LIU, Wei , KIM, Kanghyun , BOGGS, Karl , CHISM, Richard
IPC分类号： B65D77/04 , B65D25/14 , B65D85/84 , B67D7/58 , H01L21/02
摘要： The present disclosure relates to a blow-molded, rigid collapsible liner that can be suitable particularly for smaller storage and dispensing systems. The rigid collapsible liner may be a stand-alone liner, e.g., used without an outer container, and may be dispensed from a fixed pressure dispensing can. Folds in the rigid collapsible liner may be substantially eliminated, thereby substantially reducing or eliminating the problems associated with pinholes, weld tears, and overflow. The present disclosure also relates to flexible gusseted or non-gusseted liners, which is scalable in size and may be used for storage of up to 200 L or more. The flexible gusseted liner may be foldable, such that the liner can be introduced into a dispensing can. The liner can be made of thicker materials, substantially reducing or eliminating the problems associated pinholes, and may include more robust welds, substantially reducing or eliminating the problems associated weld tears.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式