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1. 发明公开

EP0903784A3 Improved techniques for forming electrically blowable fuses on an integrated circuit 失效
标题翻译：改进的技术，以形成在集成电路上的电可编程熔丝
公开(公告)号：EP0903784A3
公开(公告)日：2005-03-23
申请号：EP98112434.0
申请日：1998-07-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Weigand, Peter , Tobben, Dirk
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an electrically blowable fuse on a semiconductor substrate. The method includes forming a fuse portion 102 on the semiconductor substrate. The fuse portion is configured to turn substantially non-conductive when a current exceeding a predefined current level passes through the fuse portion. The method also includes depositing a substantially conformal first layer 302 of dielectric material above the fuse portion and depositing a second layer 304 of dielectric material above the first layer, thereby forming a protrusion of dielectric material above the fuse portion. The second layer being different from the first layer. The method further includes performing chemical-mechanical polish on the protrusion to form an opening through the second layer above the protrusion. There is also included etching, in a substantially isotropic manner, a portion of the first layer through the opening to form a microcavity 502 about the fuse portion. The etching is substantially selective to the second layer and the fuse portion. Additionally, there is included depositing a substantially conformal third layer 606 of dielectric material above the second layer, thereby closing the opening in the second layer.

2. 发明公开

EP0911878A3 Metalization system 失效
标题翻译： Metallisierungssystem
公开(公告)号：EP0911878A3
公开(公告)日：2001-04-04
申请号：EP98113441.4
申请日：1998-07-18
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Weigand, Peter , Tobben, Dirk
IPC分类号： H01L23/532
CPC分类号： H01L23/5329 , H01L2924/0002 , H05K1/0201 , H05K3/4644 , H05K3/4676 , H01L2924/00
摘要： A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition. Thus, the leads of the next metalization layer will be deposited directly on the diamond or sapphire layer which will serve as an etch stop during the metal etching process.

3. 发明公开

EP0911878A2 Metalization system 失效
标题翻译： Metallisierungssystem
公开(公告)号：EP0911878A2
公开(公告)日：1999-04-28
申请号：EP98113441.4
申请日：1998-07-18
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Weigand, Peter , Tobben, Dirk
IPC分类号： H01L23/532
CPC分类号： H01L23/5329 , H01L2924/0002 , H05K1/0201 , H05K3/4644 , H05K3/4676 , H01L2924/00
摘要： A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition. Thus, the leads of the next metalization layer will be deposited directly on the diamond or sapphire layer which will serve as an etch stop during the metal etching process.
摘要翻译：一种具有包括金刚石或蓝宝石层22的复合介电层的多级集成电路金属化系统。多个图案化金属化层设置在半导体衬底10的上方。复合电介质层设置在一对金属化层之间。复合介电层22包括一层金刚石或蓝宝石。金刚石或蓝宝石层在其表面上设置有图案化的金属化层之一。导电通孔34通过复合层。导电通孔的一端与金刚石或蓝宝石层接触。金刚石或蓝宝石层沿着设置在其上的金属化层横向导热至由导电通孔提供的散热片。图案化的金刚石或蓝宝石层在第二次金属化沉积期间提供掩模。因此，下一个金属化层的引线将直接沉积在金刚石或蓝宝石层上，该金属或蓝宝石层将在金属蚀刻工艺期间用作蚀刻停止层。

4. 发明公开

EP0875928A2 Metallization in semiconductor devices 失效
标题翻译： Metallisierung在Halbleitervorrichtungen
公开(公告)号：EP0875928A2
公开(公告)日：1998-11-04
申请号：EP98104745.9
申请日：1998-03-17
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Tobben, Dirk , Spuler, Bruno , Gutsche, Martin , Weigand, Peter
IPC分类号： H01L21/768 , H01L21/321
CPC分类号： H05K3/061 , H01L21/32139 , H01L21/76838 , H05K1/0284 , H05K2201/09018 , H05K2203/0585
摘要： A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.
摘要翻译：一种在基板上形成多根导电线的方法。该方法包括在衬底的表面上形成相对非平面的金属层。在金属层上沉积自平面化材料。自平面化材料在金属层的表面上形成平坦化层。与相对非平面的金属层相比，平坦化层具有相对平坦的表面。在平坦化层的表面上沉积光致抗蚀剂层。光刻胶层用多个凹槽构图以形成掩模，该凹槽暴露出平坦化层的下部。光致抗蚀剂掩模用作掩模以蚀刻平坦化层的暴露部分中的凹槽，从而形成第二掩模。第二掩模暴露相对非平面金属层的下层部分。第二掩模用于蚀刻相对非平面导电金属层中的凹槽，从而在金属层中形成多个导电线。电线通过在相对非平面的金属层中形成的凹槽彼此分离。平面化层是通过旋涂有机聚合物，例如具有硅的有机聚合物，或可流动的氧化物，或氢化二恶烷，或二乙烯基 - 硅氧烷 - 苯并环丁烯形成的。使用反应离子蚀刻蚀刻金属层。使用湿化学蚀刻去除平坦化层。

5. 发明公开

EP0924762A2 Interconnections in integrated circuit devices 审中-公开
标题翻译： Leertbahnen in integrierten Schaltungen
公开(公告)号：EP0924762A2
公开(公告)日：1999-06-23
申请号：EP98121303.6
申请日：1998-11-09
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Bergner, wolfgang , Gall, Martin , Weigand, Peter
IPC分类号： H01L23/528 , H01L21/321
CPC分类号： H01L21/7684 , H01L21/3212 , H01L23/528 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： For use in a damascene process for forming the conductive interconnection network of an integrated circuit device, the relatively wide trenches (21) in an insulating layer (20A, 20B) are provided with arrays of insulating plugs 22 to avoid dishing in the metallic conductive paths when chemical mechanical polishing is used to planarize the surface.
摘要翻译：为了在用于形成集成电路器件的导电互连网络的镶嵌工艺中使用，绝缘层（20A，20B）中相对宽的沟槽（21）设置有绝缘插头22的阵列，以避免金属导电路径中的凹陷当化学机械抛光用于平坦化表面时。

6. 发明公开

EP0903784A2 Improved techniques for forming electrically blowable fuses on an integrated circuit 失效
标题翻译：改进的技术，以形成在集成电路上的电可编程熔丝
公开(公告)号：EP0903784A2
公开(公告)日：1999-03-24
申请号：EP98112434.0
申请日：1998-07-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Weigand, Peter , Tobben, Dirk
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an electrically blowable fuse on a semiconductor substrate. The method includes forming a fuse portion 102 on the semiconductor substrate. The fuse portion is configured to turn substantially non-conductive when a current exceeding a predefined current level passes through the fuse portion. The method also includes depositing a substantially conformal first layer 302 of dielectric material above the fuse portion and depositing a second layer 304 of dielectric material above the first layer, thereby forming a protrusion of dielectric material above the fuse portion. The second layer being different from the first layer. The method further includes performing chemical-mechanical polish on the protrusion to form an opening through the second layer above the protrusion. There is also included etching, in a substantially isotropic manner, a portion of the first layer through the opening to form a microcavity 502 about the fuse portion. The etching is substantially selective to the second layer and the fuse portion. Additionally, there is included depositing a substantially conformal third layer 606 of dielectric material above the second layer, thereby closing the opening in the second layer.
摘要翻译：一种在电可熔断熔丝上的半导体衬底的制造方法。该方法包括形成在所述半导体衬底的熔丝部分102。熔丝部分被配置为当电流超过预定的电流电平通过熔丝部分打开基本不导电。因此，该方法包括沉积在熔丝部分上面的介电材料的基本保形的第一层302和沉积在第一层之上的介电材料的第二层304，由此形成电介质材料的熔丝部分上方的突出部。所述第二层与所述第一层不同。该方法包括在所述突出部进行进一步的化学机械抛光，以在通过所述突出部上方的第二层的开口。因此，存在被包括蚀刻，以基本上各向同性的方式，通过所述开口的所述第一层的一部分，以形成约熔丝部分502的微腔。蚀刻基本上有选择性的第二层和熔丝部分。此外，还有被包括沉积所述第二层上方的介电材料606的基本保形的第三层，由此封闭第二层中的开口。

7. 发明公开

EP0875930A2 Planarization of an interconnection structure 失效
标题翻译： Planarisierung einer Leiterbahnstruktur
公开(公告)号：EP0875930A2
公开(公告)日：1998-11-04
申请号：EP98105151.9
申请日：1998-03-21
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Ilg, Matthias , Tobben, Dirk , Weigand, Peter
IPC分类号： H01L21/768 , H01L21/3105
CPC分类号： H01L21/76819 , H01L21/31051 , H01L21/31053
摘要： A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region. The method is used for filling gaps, such as gaps between adjacent gate electrodes formed in a gate electrode surface region of a semiconductor structure.
摘要翻译：一种用于平面化具有高纵横比拓扑的第一表面区域和具有低纵横比拓扑的第二表面区域的半导体结构的方法。可流动的材料沉积在结构的第一和第二表面区域上。材料的一部分填充高纵横比拓扑中的间隙，以在高纵横比拓扑上形成基本平坦的表面。在可流动氧化物材料上形成掺杂层，例如磷掺杂玻璃。掺杂层设置在高纵横比和低纵横比区域之上。低纵横比区域上的上表面部分高于可流动材料的上表面。在第一和第二表面部分上去除掺杂层的上部，以形成在高纵横比区域和低纵横比区域之上具有基本平坦表面的层。该方法用于填充间隙，例如形成在半导体结构的栅电极表面区域中的相邻栅电极之间的间隙。

8. 发明公开

EP0825645A1 Gapfill and planarization process for shallow trench isolation 失效
标题翻译： Lückenfüllungs-und Planarisierungsverfahrenfürflache Grabenisolation
公开(公告)号：EP0825645A1
公开(公告)日：1998-02-25
申请号：EP97306000.7
申请日：1997-08-07
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Weigand, Peter
IPC分类号： H01L21/762 , H01L21/3105
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.
摘要翻译：描述了一种用绝缘材料在集成电路的半导体衬底中填充浅沟槽隔离（STI）沟槽并将所得结构平坦化到集成电路的相邻部分的水平的方法。该方法包括在半导体衬底的非有源区中形成沟槽，在沟槽中和在半导体衬底的表面上沉积氧化物层，以及从集成电路结构的有源区去除氧化物，填充的浅沟槽隔离结构相对于集成电路结构的其余部分具有基本平坦的形貌。

9. 发明公开

EP1073096A1 Semiconductor workpiece processing apparatus and method 有权
标题翻译： Bearbeitung eineHalbleiterwerkstückes
公开(公告)号：EP1073096A1
公开(公告)日：2001-01-31
申请号：EP00115094.5
申请日：2000-07-27
申请人： KABUSHIKI KAISHA TOSHIBA , SIEMENS AKTIENGESELLSCHAFT
发明人： Shoda, Naohiro , Weigand, Peter
IPC分类号： H01L21/00
CPC分类号： H01L21/67109 , H01L21/6831
摘要： A wafer processing apparatus includes a processing chamber, a chuck (104) arranged in the processing chamber for supporting a wafer (Wafer), and a pedestal (102) which is spaced apart from the chuck. A first gas layer is provided between the chuck and the wafer and a second gas layer is provided in the space between the pedestal and the chuck. The pressure of the first gas layer is controlled to be in a pressure range in which a thermal conductivity of the first gas layer is substantially constant with respect changes in pressure of the first gas layer and the pressure of the second gas layer is controlled so as to control an amount of heat transferred to/from the pedestal.
摘要翻译：晶片处理装置包括处理室，布置在处理室中用于支撑晶片（晶片）的卡盘（104）和与卡盘间隔开的基座（102）。在卡盘和晶片之间设置第一气体层，并且在基座和卡盘之间的空间中设置第二气体层。将第一气体层的压力控制在第一气体层的热传导率相对于第一气体层的压力变化大致恒定的压力范围，第二气体层的压力被控制为以控制传递到/从基座的热量。

10. 发明公开

EP0905778A2 Improved multi-level conductive structure and methods therefor 审中-公开
标题翻译： Verbesserte Mehrlagenleitungsstruktur und Verfahrendafür
公开(公告)号：EP0905778A2
公开(公告)日：1999-03-31
申请号：EP98116755.4
申请日：1998-09-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Tobben, Dirk , Weigand, Peter
IPC分类号： H01L23/532
CPC分类号： H01L23/5329 , H01L21/76831 , H01L21/76834 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multi-level conductive structure on an integrated circuit. The method includes forming a first conductive layer 108 and forming a first dielectric layer 112 above the first conductive layer. The method further includes forming a second conductive layer 302 above the first dielectric layer. There is also included etching through the second conductive layer and at least partially into the first dielectric layer to form a trench 706 in the second conductive layer and the first dielectric layer, thereby removing at least a portion of the dielectric layer and forming a first conductive line 503 and a second conductive line 505 in the second conductive layer. Further, the method includes depositing a low capacitance material 908 into the trench. The low capacitance material represents a material having a dielectric constant lower than a dielectric constant of the first dielectric layer.
摘要翻译：一种在集成电路上形成多层导电结构的方法。该方法包括形成第一导电层108并在第一导电层上方形成第一介电层112。该方法还包括在第一介电层上形成第二导电层302。还包括通过第二导电层蚀刻并且至少部分地进入第一介电层以在第二导电层和第一介电层中形成沟槽706，由此去除介电层的至少一部分并形成第一导电线503和在第二导电层中的第二导线505。此外，该方法包括将低电容材料908沉积到沟槽中。低电容材料表示介电常数低于第一介电层的介电常数的材料。

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