专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO0017772A3 CONFIGURABLE HARDWARE BLOCK 审中-公开
标题翻译：配置硬件BLOCK
公开(公告)号：WO0017772A3
公开(公告)日：2000-07-27
申请号：PCT/DE9902891
申请日：1999-09-10
申请人： SIEMENS AG , ARNOLD RALF , KLEVE HELGE , SIEMERS CHRISTIAN
发明人： ARNOLD RALF , KLEVE HELGE , SIEMERS CHRISTIAN
IPC分类号： G06F11/00 , G06F9/30 , G06F9/302 , G06F9/318 , G06F15/78 , H03K19/173
CPC分类号： G06F9/3001 , G06F15/7867
摘要： The invention relates to a configurable hardware block which is designed to read data stored in a storage means according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the storage means. The hardware block described is characterized in that it is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.
摘要翻译：中描述了一种可配置的硬件块，其适于根据其配置在存储装置中，以算术和/或逻辑处理该读出的数据读出存储数据，以及向表示在处理数据的结果写入所述存储装置。所描述的硬件块，其特征在于它是在一个位置与外部硬件交互移动。这提供了灵活的和普遍适用的硬件块。

2. 发明申请

WO0017771A3 METHOD FOR CONFIGURING CONFIGURABLE HARDWARE BLOCKS 审中-公开
标题翻译：方法来配置可配置硬件模块
公开(公告)号：WO0017771A3
公开(公告)日：2000-08-17
申请号：PCT/DE9902878
申请日：1999-09-10
申请人： SIEMENS AG , ARNOLD RALF , KLEVE HELGE , SIEMERS CHRISTIAN
发明人： ARNOLD RALF , KLEVE HELGE , SIEMERS CHRISTIAN
IPC分类号： G06F9/318 , G06F9/302 , G06F9/38 , G06F15/78 , G06F17/50
CPC分类号： G06F9/3001 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： The invention relates to various methods for configuring configurable hardware blocks. The methods are especially characterized by generation of the configuration data used to configure the hardware blocks. The methods described for generating configuration data enable configuration data to be generated and allow hardware blocks to be configured easily, quickly and efficiently using said configuration data.
摘要翻译：有配置描述的配置的硬件模块的各种方法。所述方法的特征尤其在于由生成配置数据的，这可以使用硬件块来配置。所描述的配置数据生成两个结构数据生成本身，并使用该配置的硬件块的配置，数据能够容易地快速地和有效地进行。

3. 发明申请

WO2005052612A3 INPUT AND OUTPUT CIRCUIT FOR AN INTEGRATED SWITCHING CIRCUIT, METHOD FOR TESTING AN INTEGRATED SWITCHING CIRCUIT AND AN INTEGRATED SWITCHING CIRCUIT PROVIDED WITH SAID INPUT AND OUTPUT CIRCUIT 审中-公开
标题翻译：集成电路，检验方法集成电路和集成电路这样的输入输出电路的输入和输出电路
公开(公告)号：WO2005052612A3
公开(公告)日：2005-11-17
申请号：PCT/DE2004002588
申请日：2004-11-23
申请人： INFINEON TECHNOLOGIES AG , ARNOLD RALF , GLAS MARTIN , MUELLER CHRISTIAN , OBERLE HANS-DIETER
发明人： ARNOLD RALF , GLAS MARTIN , MUELLER CHRISTIAN , OBERLE HANS-DIETER
IPC分类号： G01R31/3185
CPC分类号： G01R31/318566 , G01R31/318572
摘要： The invention relates to an input-output circuit (2) for an integrated switching circuit comprising at least one signal connection (PAD) for an external contact, a protection circuit (ESD), an input driver (IN) and an output driver (OUT). The inventive input-output circuit (2) also comprises an additional circuit (22, 31, 51) whose first input is connected to the signal connection (PAD) by the protection circuit (ESD) and a test value for the input-output circuit (2-5) arranged at the output of the additional circuit.
摘要翻译：根据本发明的集成电路的发明（2）的输入和输出电路包括用于外部接触的至少一个信号端子（PAD），保护电路（ESD），驾驶员输入（IN）和输出驱动器（OUT）。此外，本发明的输入和输出电路通过附加的电路包括：（2）（22; 31; 51），其具有经由所述保护电路（ESD）到信号端（PAD）的第一输入端和在其输出端的测试值的函数输入和输出电路（2-5）被施加。

4. 发明申请

WO2005015249A3 ELECTRONIC ELEMENT COMPRISING AN ELECTRONIC CIRCUIT WHICH IS TO BE TESTED AND TEST SYSTEM ARRANGEMENT WHICH IS USED TO TEST THE ELECTRONIC ELEMENT 审中-公开
标题翻译： WITH A，电子元件，以测试结束电子电路测试系统安排用于测试的电子元
公开(公告)号：WO2005015249A3
公开(公告)日：2005-03-31
申请号：PCT/DE2004001493
申请日：2004-07-08
申请人： INFINEON TECHNOLOGIES AG , ARNOLD RALF , OSSIMITZ PETER
发明人： ARNOLD RALF , OSSIMITZ PETER
IPC分类号： G01R31/3185
CPC分类号： G01R31/318555 , G01R31/318566
摘要： The invention relates to an electronic element comprising an electronic circuit which is to be tested and a comparator circuit. Said comparator circuit comprises first input terminals, whereby each outlet of the electronic circuit which is to be tested is coupled to a first input terminal, also comprising second input terminals which are used to feed target value signals and at least one outlet terminal. Said comparator circuit is configured in such a way that the actual value signals are compared to the target value signals and the electronic element is configured in such a manner that it processes signals of a 3-value logic. The results of said comparison can be produced on the at least one output terminal of the comparator circuit.
摘要翻译：一种电子元件具有测试电子电路和比较电路。所述比较器具有第一输入端子，每个测试电子电路的输出端被耦合到第一输入终端，和用于供给目标值信号的第二输入端子和至少一个输出端。该比较器被构造为使得其与所述的设定点的信号的实际值的信号进行比较，并且其中所述电子元件被进一步构造成使得其处理一个三值逻辑的信号。比较的结果可提供给比较器电路的至少一个输出端。

5. 发明申请

WO2009036941A3 BINARY BLAZED DIFFRACTIVE OPTICAL ELEMENT 审中-公开
标题翻译：二进制闪耀衍射光学元件
公开(公告)号：WO2009036941A3
公开(公告)日：2009-05-28
申请号：PCT/EP2008007661
申请日：2008-09-16
申请人： ZEISS CARL AG , ARNOLD RALF , KLEEMANN BERND , RUOFF JOHANNES
发明人： ARNOLD RALF , KLEEMANN BERND , RUOFF JOHANNES
IPC分类号： G02B5/18
CPC分类号： G02B5/1819 , G02B5/1833 , G02B5/189
摘要： The invention relates to a binary blazed diffractive optical element (10) comprising a plurality of diffractive structures (16) which extend substantially parallel to one another and have a width g that runs perpendicularly to the extension direction and is greater than the effective wavelength of the electromagnetic radiation for which the diffractive optical element (10) is optimised. Each diffractive structure (16) comprises a row of individual sub-structures (18), which when viewed from above take the form of a closed geometric surface. The dimension of said surface running parallel to the extension of the diffractive structures (16) varies perpendicularly to the extension direction of the diffractive structures (16) and the dimension running perpendicularly to the extension of the diffractive structures (16) is greater than the effective wavelength. According to the invention, the individual sub-structures (18) have birefringent structures (26) which reduce the polarisation dependency of the diffraction efficiency of the diffractive optical element (10).
摘要翻译：二进制闪耀衍射光学元件（10）具有多个衍射结构（16），其基本上平行于彼此延伸，并垂直于其延伸方向的宽度为g，这比所述电磁辐射的有效波长更大的到该衍射光学元件（10）被优化。衍射结构（16）的每一个包括多个单独的子结构（18）具有封闭的几何面积的在平面图中的形状，其平行于所述衍射结构的所述延伸部（16）引导senkecht尺寸的方向衍射结构的延伸方向（16）而不同，并且其垂直于所述衍射结构（16）的延伸部引导尺寸比有效波长。 Erfindungsgeimäß各个子结构（18）采取的形式双折射结构（26），由此所述衍射光学元件（10）的衍射效率的偏振依赖性降低。

6. 发明申请

WO2005114101A8 METHOD OF MANUFACTURING AN OPTICAL ELEMENT 审中-公开
标题翻译：制造光学元件的方法
公开(公告)号：WO2005114101A8
公开(公告)日：2006-02-09
申请号：PCT/EP2004005194
申请日：2004-05-14
申请人： ZEISS CARL SMT AG , ARNOLD RALF , DOERBAND BERND , SCHILLKE FRANK , BEDER SUSANNE
发明人： ARNOLD RALF , DOERBAND BERND , SCHILLKE FRANK , BEDER SUSANNE
IPC分类号： G01B11/24 , B24B13/015 , B24B49/12
CPC分类号： G01B11/2441
摘要： A method of manufacturing an optical element (5) includes testing the optical element (5) by using an interferometer optics (1) generating a beam (13) of measuring light illuminating only a sub-aperture of the tested optical element (5). The interferometer optics (1) comprises a hologram. Results of the sub-aperture measurement are stitched together to obtain a measuring result with respect to the full surface of the optical element (5). Further, a method of calibrating the interferometer optics (1) includes performing an interferometric measurement using a calibrating optics having a hologram covering only a sub-aperture of the full cross section of the beam (13) of measuring light generated by the interferometer optics (1) and stitching together the sub-aperture measurements to obtain a result indicative for the full cross section of the interferometer optics (1).
摘要翻译：制造光学元件（5）的方法包括通过使用产生仅照射被测光学元件（5）的子孔径的光的光束（13）的干涉仪光学元件（1）来测试光学元件（5）。干涉仪光学器件（1）包括全息图。将子孔径测量的结果缝合在一起以获得关于光学元件（5）的整个表面的测量结果。此外，校准干涉仪光学器件（1）的方法包括使用校准光学器件执行干涉测量，所述校准光学器件具有仅覆盖光束（13）的全横截面的子孔径的测量由干涉仪光学器件产生的光的全息图（ 1）并且将子孔径测量结合在一起以获得指示干涉仪光学器件（1）的全部横截面的结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式