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1. 发明公开

EP0664512A1 Design for testability technique of CMOS and BiCMOS ICs 失效
标题翻译： Verfahren zumprüfgerechtenEntwurf von CMOS和BICMOS IC。
公开(公告)号：EP0664512A1
公开(公告)日：1995-07-26
申请号：EP94830023.1
申请日：1994-01-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Penza Luigi , Favalli Michele , Ricco' Bruno
IPC分类号： G06F11/24
CPC分类号： G01R31/3008 , G01R31/3004 , G01R31/3012 , G01R31/31704
摘要： A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected BICSs avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional I DDQ test. In a modified embodiment, a DFT scheme of the invention may be adapted to reveal also stuck-at faults, by connecting together the output nodes of certain monitoring inverters to create activatable current paths from a test node ( shadow line ) and a supply rail of the IC.
摘要翻译：用于检测CMOS和BiCMOS逻辑IC中的桥接故障的DFT技术，采用由要测试的功能电路的信号节点驱动的专门集成的监控逆变器，用于显示临界值的中间电压的存在。监控逆变器通过专用阴影线提供，专用阴影线通过负载：用于静态实现的电阻或用于动态（时钟））实现的电阻连接到功能电路的任一个的电源轨。无串联连接的BICS避免了功能电路性能的恶化，并兼容缩减电源和在线测试技术。只有关键的桥接故障可以被可靠和有选择地检测，从而减少了拒绝的数量，不能进行常规的IDDQ测试。在修改的实施例中，本发明的DFT方案可以适于通过将某些监控逆变器的输出节点连接在一起以产生可测试的电流路径，从测试节点（阴影线）和供电轨 IC。

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