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1. 发明申请

US20160049447A1 RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件和操作电阻式存储器件的方法
公开(公告)号：US20160049447A1
公开(公告)日：2016-02-18
申请号：US14736525
申请日：2015-06-11
申请人： SEUNG-JAE JUNG , YOUN-SEON KANG , JUNG-DAL CHOI
发明人： SEUNG-JAE JUNG , YOUN-SEON KANG , JUNG-DAL CHOI
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/224 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.
摘要翻译：电阻式存储器件包括沿一个方向排列成一行的多个存储器单元柱，每个存储单元柱具有连接到存储层的存储层和顶部电极层，顶部导电线具有向下延伸的多个突起，在顶部导线的底部被限定，以及多个绝缘柱。上导电线面的突起分别电连接到存储单元柱，以便通过存储单元柱的顶电极电连接到存储层。绝缘柱从记忆层的侧壁表面和存储单元柱的顶部电极层之间的绝缘空间延伸到顶部导电线的底部中的凹穴中。

2. 发明申请

US20160181321A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20160181321A1
公开(公告)日：2016-06-23
申请号：US14963947
申请日：2015-12-09
申请人： SEUNG-JAE JUNG , YOUN-SEON KANG
发明人： SEUNG-JAE JUNG , YOUN-SEON KANG
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L45/147 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/16
摘要： A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.
摘要翻译：可变电阻存储器件包括多个第一导线，每个第一导线沿第一方向延伸，多个第二导线位于第一导线之上，并且每个第二导线沿第二方向延伸横向于第一个方向。多个第一存储单元位于第一和第二导线彼此重叠的交点处，每个第一存储单元包括具有第一可变电阻图案，第一牺牲图案和第二可变电阻图案的第一可变电阻结构，在第一平面上沿第一方向堆叠。多个第三导线在第二导线之上，第三导线中的每一根在第一方向上延伸，并且多个第二存储单元位于第二和第三导线彼此重叠的交点处。每个第二存储单元包括第二可变电阻结构，其具有第三可变电阻图案，第二牺牲图案和第四可变电阻图案，其顺序地在第二平面上沿第一方向堆叠。

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