专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11908947B2 Semiconductor device 有权
公开(公告)号：US11908947B2
公开(公告)日：2024-02-20
申请号：US17628091
申请日：2020-07-27
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Munehiro Kozuma , Takahiko Ishizu , Takeshi Aoki , Masashi Fujita , Kazuma Furutani , Kousuke Sasaki
IPC分类号： G11C7/10 , H01L29/786 , G06F7/544 , G11C7/12 , G11C7/14 , H10B12/00 , H01L27/12
CPC分类号： H01L29/7869 , G06F7/5443 , G11C7/1069 , G11C7/1096 , G11C7/12 , G11C7/14 , H10B12/50 , H01L27/1225
摘要： A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

2. 发明授权

US09972389B2 Method for operating semiconductor device 有权
公开(公告)号：US09972389B2
公开(公告)日：2018-05-15
申请号：US15450147
申请日：2017-03-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Tsubuku , Masashi Fujita
IPC分类号： G11C5/06 , G11C14/00 , G11C13/00
CPC分类号： G11C14/0045 , G11C11/401 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/74 , G11C2213/79
摘要： Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

3. 发明授权

US09490267B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09490267B2
公开(公告)日：2016-11-08
申请号：US14598384
申请日：2015-01-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Masashi Fujita , Yutaka Shionoiri , Hiroyuki Tomatsu , Hidetomo Kobayashi
IPC分类号： H01L27/12 , H01L21/84 , H01L27/115 , H01L27/088 , H01L27/108
CPC分类号： H01L27/1225 , H01L21/84 , H01L27/088 , H01L27/108 , H01L27/1156 , H01L27/1203 , H01L27/1222 , H01L27/1251
摘要： A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.
摘要翻译：提供在绝缘区域上方设置有在第一半导体区域和第二半导体区域上设置绝缘区域的衬底上的第一场效应晶体管; 设置在所述基板上的绝缘层; 第二场效应晶体管，其设置在所述绝缘层的一个平面上，并且包括氧化物半导体层; 并提供控制终端。控制端子形成在与第二场效应晶体管的源极和漏极相同的步骤中，并且用于控制第一场效应晶体管的阈值电压的电压被提供给控制端子。

4. 发明授权

US09043561B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US09043561B2
公开(公告)日：2015-05-26
申请号：US13873388
申请日：2013-04-30
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Fujita
IPC分类号： G06F12/08 , G11C16/00 , G11C11/412 , G11C11/413
CPC分类号： G06F12/0808 , G06F12/0895 , G11C11/412 , G11C11/413 , G11C11/417 , G11C16/00 , Y02D10/13
摘要： To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit.
摘要翻译：提供低功耗的存储设备。存储装置包括多个高速缓存行。每个高速缓存行包括存储高速缓存数据的数据字段; 存储对应于高速缓存数据的地址数据的标签; 以及存储指示存储在数据字段中的高速缓存数据是有效还是无效的有效数据的有效位。基于存储在有效位中的有效数据来确定是否向标签提供电力以及每个高速缓存行中的数据字段。

5. 发明授权

US11750194B2 Semiconductor device 有权
公开(公告)号：US11750194B2
公开(公告)日：2023-09-05
申请号：US17150859
申请日：2021-01-15
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
IPC分类号： H03K19/173 , H03K19/17728 , H03K19/17772 , H03K19/17758
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17758 , H03K19/17772
摘要： An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

6. 发明授权

US09704893B2 Semiconductor device and electronic device 有权
公开(公告)号：US09704893B2
公开(公告)日：2017-07-11
申请号：US15227009
申请日：2016-08-03
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Fujita
IPC分类号： G09G3/00 , H01L27/32 , H01L27/12
CPC分类号： H01L27/124 , H01L27/1225 , H01L27/1255 , H01L27/3244 , H01L29/78648 , H01L29/7869 , H01L29/78696
摘要： A low-power-consumption semiconductor device or the like is provided. Charge is accumulated in a node connected to a capacitor for a certain period to perform a current-voltage conversion. A gate of a transistor is connected to the node and the potential of one of a source and a drain of the transistor is changed gradually or continuously so that the potential is read when the transistor is turned on. The threshold voltage of the transistor and the capacitance value of the node are measured, so that the current-voltage conversion is performed more precisely.

7. 发明授权

US09633710B2 Method for operating semiconductor device 有权
公开(公告)号：US09633710B2
公开(公告)日：2017-04-25
申请号：US14996635
申请日：2016-01-15
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Tsubuku , Masashi Fujita
IPC分类号： G11C5/06 , G11C11/401 , G11C13/00
CPC分类号： G11C14/0045 , G11C11/401 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/74 , G11C2213/79
摘要： Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

8. 发明授权

US09355687B2 Storage circuit 有权
标题翻译：存储电路
公开(公告)号：US09355687B2
公开(公告)日：2016-05-31
申请号：US14306310
申请日：2014-06-17
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Fujita
IPC分类号： G11C11/42 , G11C5/14 , G11C14/00 , G11C29/50 , G11C5/06
CPC分类号： G11C5/14 , G11C5/06 , G11C14/00 , G11C14/0054 , G11C29/50004
摘要： A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.
摘要翻译：存储电路包括易失性存储部分，其中数据信号的存储由时钟信号和反相时钟信号控制，以及非易失性存储部分，其中提供给易失性存储部分的数据信号即使在供给电源电压停止。提供电源电压并连接到为提供时钟信号的布线提供的保护电路的布线与提供电源电压并连接到存储电路的布线分开设置。提供给与保护电路连接的布线的电源电压的停止和重新开始的定时不同于提供给连接到存储电路的布线的电源电压的停止和重新开始。

9. 发明授权

US09064599B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US09064599B2
公开(公告)日：2015-06-23
申请号：US14333582
申请日：2014-07-17
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Fujita
IPC分类号： G11C11/34 , G11C14/00 , G11C11/40 , G11C7/20 , G11C7/00 , H01L29/786 , G11C5/00 , G11C5/06 , H01L29/788 , H01L29/792
CPC分类号： G11C11/40 , G11C5/005 , G11C5/06 , G11C7/00 , G11C7/20 , G11C11/34 , G11C14/00 , G11C14/0009 , G11C14/0054 , H01L29/7869 , H01L29/788 , H01L29/792
摘要： While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.
摘要翻译：在电源供应停止的情况下，可以将保持在易失性存储部中的数据信号保持在非易失性存储部。在非易失性存储器部分中，具有极低截止电流的晶体管允许数据信号长时间保持在电容器中。因此，即使在停止供电时，非易失性存储部也能够保持逻辑状态。当再次开始供电时，在电源供应停止时保持在电容器中的数据信号被设定为通过接通复位电路而不发生故障的电位。

10. 发明申请

US20150016179A1 MEMORY CIRCUIT 有权
标题翻译：存储器电路
公开(公告)号：US20150016179A1
公开(公告)日：2015-01-15
申请号：US14333582
申请日：2014-07-17
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Masashi Fujita
IPC分类号： G11C11/40 , G11C14/00 , H01L29/786
CPC分类号： G11C11/40 , G11C5/005 , G11C5/06 , G11C7/00 , G11C7/20 , G11C11/34 , G11C14/00 , G11C14/0009 , G11C14/0054 , H01L29/7869 , H01L29/788 , H01L29/792
摘要： While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.
摘要翻译：在电源供应停止的情况下，可以将保持在易失性存储部中的数据信号保持在非易失性存储部。在非易失性存储器部分中，具有极低截止电流的晶体管允许数据信号长时间保持在电容器中。因此，即使在停止供电时，非易失性存储部也能够保持逻辑状态。当再次开始供电时，在电源供应停止时保持在电容器中的数据信号被设定为通过接通复位电路而不发生故障的电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式