专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11037903B2 Plasma etch singulated semiconductor packages and related methods 有权
公开(公告)号：US11037903B2
公开(公告)日：2021-06-15
申请号：US15395181
申请日：2016-12-30
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Darrell Truhitte
IPC分类号： H01L21/00 , H01L23/00 , H01L21/78 , H01L23/544 , H01L21/48 , H01L21/56 , H01L21/311
摘要： A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.

2. 发明授权

US11049843B2 Semiconductor packages 有权
公开(公告)号：US11049843B2
公开(公告)日：2021-06-29
申请号：US16387958
申请日：2019-04-18
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Phillip Celaya , James P. Letterman, Jr. , Robert L. Marquis , Darrell Truhitte
IPC分类号： H01L23/00 , H01L23/495 , H01L23/31 , H01L21/56 , H01L21/78 , H01L21/48 , H01L21/02
摘要： Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

3. 发明授权

US10304798B2 Semiconductor packages with leadframes and related methods 有权
公开(公告)号：US10304798B2
公开(公告)日：2019-05-28
申请号：US15870215
申请日：2018-01-12
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Phillip Celaya , James P. Letterman, Jr. , Robert L. Marquis , Darrell Truhitte
IPC分类号： H01L21/00 , H01L23/00 , H01L21/56 , H01L21/78 , H01L21/48 , H01L23/495 , H01L21/02 , H01L23/31
摘要： Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

4. 发明授权

US09899349B2 Semiconductor packages and related methods 有权
公开(公告)号：US09899349B2
公开(公告)日：2018-02-20
申请号：US15063011
申请日：2016-03-07
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Phillip Celaya , James P Letterman, Jr. , Robert L. Marquis , Darrell Truhitte
IPC分类号： H01L21/48 , H01L23/00 , H01L21/56 , H01L21/78 , H01L23/495 , H01L21/02 , H01L23/31
CPC分类号： H01L24/97 , H01L21/02021 , H01L21/4821 , H01L21/4828 , H01L21/561 , H01L21/78 , H01L23/3107 , H01L23/4952 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/05 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0401 , H01L2224/05553 , H01L2224/05599 , H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/10161 , H01L2924/19107 , H01L2924/00012 , H01L2224/45099 , H01L2224/29099
摘要： Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

5. 发明授权

US09892952B2 Wafer level flat no-lead semiconductor packages and methods of manufacture 有权
公开(公告)号：US09892952B2
公开(公告)日：2018-02-13
申请号：US14341454
申请日：2014-07-25
申请人： Semiconductor Components Industries, LLC
发明人： Darrell Truhitte , James P. Letterman, Jr.
IPC分类号： H01L21/683 , H01L23/31 , H01L21/56 , H01L21/48 , H01L23/00 , H01L23/36 , H01L23/495
CPC分类号： H01L21/6835 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/36 , H01L23/49537 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68304 , H01L2221/68327 , H01L2221/68377 , H01L2221/68381 , H01L2224/04105 , H01L2224/11 , H01L2224/11003 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/11418 , H01L2224/1146 , H01L2224/11462 , H01L2224/116 , H01L2224/119 , H01L2224/1308 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/1319 , H01L2224/16245 , H01L2224/16258 , H01L2224/27003 , H01L2224/27312 , H01L2224/2732 , H01L2224/27334 , H01L2224/27418 , H01L2224/2746 , H01L2224/27462 , H01L2224/276 , H01L2224/279 , H01L2224/2908 , H01L2224/291 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/2919 , H01L2224/32245 , H01L2224/32258 , H01L2224/33181 , H01L2224/45015 , H01L2224/48091 , H01L2224/4811 , H01L2224/48111 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/73204 , H01L2224/73265 , H01L2224/75251 , H01L2224/75252 , H01L2224/753 , H01L2224/75755 , H01L2224/75756 , H01L2224/81192 , H01L2224/8121 , H01L2224/81805 , H01L2224/81815 , H01L2224/81856 , H01L2224/83 , H01L2224/83005 , H01L2224/83191 , H01L2224/83192 , H01L2224/8321 , H01L2224/83805 , H01L2224/83815 , H01L2224/83856 , H01L2224/85005 , H01L2224/92 , H01L2224/92125 , H01L2224/92147 , H01L2224/92227 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00014 , H01L2924/181 , H01L2924/3511 , H01L2924/0665 , H01L2924/014 , H01L2224/81 , H01L2224/27 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/207
摘要： Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

6. 发明授权

US09559007B1 Plasma etch singulated semiconductor packages and related methods 有权
标题翻译：等离子蚀刻单片半导体封装及相关方法
公开(公告)号：US09559007B1
公开(公告)日：2017-01-31
申请号：US14870440
申请日：2015-09-30
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Darrell Truhitte
IPC分类号： H01L21/00 , H01L21/78 , H01L21/311 , H01L23/544 , H01L21/48
CPC分类号： H01L24/96 , H01L21/31138 , H01L21/4821 , H01L21/4828 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/78 , H01L23/544 , H01L2223/54453
摘要： A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.
摘要翻译：形成多个半导体封装的方法包括提供至少部分地封装在密封剂中的未折叠半导体封装的阵列。非引脚半导体封装的阵列可以与引线框架或衬底耦合。通过使用等离子体蚀刻工艺和与该阵列耦合的固定装置在蚀刻掩模中的狭缝，在密封剂中同时蚀刻第一多个分割线。也可以蚀刻第二多个平行分割线。第一和第二多个单行线可以包括基本上直的或弧形的线。所述第二多个平行分割线可以基本上垂直于所述第一多个并行分离线，并且使用所述等离子体蚀刻工艺，所述夹具和蚀刻掩模形成。阵列中的分割线的形成将阵列分成多个单个半导体封装。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式