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1. 发明申请

WO1993011508A1 PRINTER VIDEO PROCESSOR 审中-公开
标题翻译：打印机视频处理器
公开(公告)号：WO1993011508A1
公开(公告)日：1993-06-10
申请号：PCT/JP1992001557
申请日：1992-11-27
申请人： SEIKO EPSON CORPORATION
发明人： SEIKO EPSON CORPORATION , LENTZ, Derek, J. , YOUNG, Linley, M.
IPC分类号： G06K15/00
CPC分类号： G06K15/00 , G06K2215/0091 , G06K2215/0094
摘要： A video processor is provided for a printer controller to be situated locally to a printer. A microprocessor in the printer controller executes instructions and performs image processing, while the video processor provides for scan data fetches, serialization, and print engine synchronization as well as scan status and interrupt generation. The video processor accesses data in an external page memory, also called a frame buffer, by submitting requests to an I/O interface. Each request comprises an address with a corresponding data size. After the scan data request, the video processor updates the address and data size for the next request. Upon receipt of the requested data, the video processor sends the scan data serially to a printer engine. In order to supply an uninterrupted stream of scan data to the printer engine, the printer video processor must queue enough scan data to offset the latencies involved in processing the data requests to the page memory.
摘要翻译：为打印机控制器提供视频处理器以便位于打印机本地。打印机控制器中的微处理器执行指令并执行图像处理，而视频处理器提供扫描数据取出，串行化和打印引擎同步以及扫描状态和中断生成。视频处理器通过将请求提交到I / O接口来访问外部页面存储器（也称为帧缓冲器）中的数据。每个请求包括具有相应数据大小的地址。在扫描数据请求之后，视频处理器更新下一个请求的地址和数据大小。在接收到所请求的数据时，视频处理器将扫描数据串行发送到打印机引擎。为了向打印机引擎提供不间断的扫描数据流，打印机视频处理器必须排队足够的扫描数据以抵消处理对页面存储器的数据请求所涉及的延迟。

2. 发明申请

WO1993001565A1 SINGLE CHIP PAGE PRINTER CONTROLLER 审中-公开
标题翻译：单芯片打印机控制器
公开(公告)号：WO1993001565A1
公开(公告)日：1993-01-21
申请号：PCT/JP1992000867
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： SEIKO EPSON CORPORATION , LENTZ, Derek, J. , WANG, Johannes , DEOSARAN, Trevor , YOUNG, Linley, M. , YAP, Kian-Chin , NGUYEN, Le Trong , MATSUBAYASHI, Makoto , LAU, Te-Li
IPC分类号： G06K15/00
CPC分类号： G06F9/30018 , G06K15/00 , G06K15/02 , G06K2215/0002 , G06K2215/0005 , G06K2215/004 , G06K2215/0054 , G06K2215/0062 , G06K2215/0071 , G06K2215/0082
摘要： A page printer controller comprising an instruction processor, a printer video processor having a video port, a data and instruction cache memory, a memory controller for interconnecting the printer video processor with external memory, and with the data and instruction cache memory, and an I/O controller for interconnecting the page printer controller to an I/O bus. The printer video processor is integrated with the I/O controller and the memory interface for optimizing memory bandwidth and allowing priority memory access. The instruction processor interfaces with a host computer through the I/O bus. The instruction processor includes pixel modification circuitry, orthogonal rotator circuitry, and bit/byte mirror circuitry. The printer video processor interfaces with the instruction processor through the I/O bus, and interfaces with memory through the memory interface. The printer video processor also controls a printer through the video port.
摘要翻译：一种页面打印机控制器，包括指令处理器，具有视频端口的打印机视频处理器，数据和指令高速缓存存储器，用于将打印机视频处理器与外部存储器互连的存储器控制器，以及数据和指令高速缓冲存储器，以及I / O控制器，用于将页面打印机控制器与I / O总线互连。打印机视频处理器与I / O控制器和存储器接口集成，以优化存储器带宽并允许优先级存储器访问。指令处理器通过I / O总线与主机连接。指令处理器包括像素修改电路，正交旋转电路和位/字节镜电路。打印机视频处理器通过I / O总线与指令处理器进行接口，并通过存储器接口与存储器进行接口。打印机视频处理器还通过视频端口控制打印机。

3. 发明申请

WO1993011500A1 PIXEL MODIFICATION UNIT 审中-公开
标题翻译：像素修改单元
公开(公告)号：WO1993011500A1
公开(公告)日：1993-06-10
申请号：PCT/JP1992001559
申请日：1992-11-27
申请人： SEIKO EPSON CORPORATION
发明人： SEIKO EPSON CORPORATION , LENTZ, Derek, J. , YOUNG, Linley, M.
IPC分类号： G06F15/66
CPC分类号： G06F9/30141 , G06F9/30043 , G06F9/30109 , G06T1/20
摘要： A pixel modification unit is provided for carrying out a variety of raster graphic manipulations in a RISC graphics processor. The pixel modification unit comprises a logic function unit, a masking unit, and a byte mirror unit. The logic function unit can perform any of 16 different logic operations between each bit of a source operand and a destination operand. The source operand may be a bit map fixed data, while the destination operand is pixel data in the bit map corresponding to the graphics image to be modified. The masking unit can mask any or all bits of a destination operand so that the logic function unit does not operate on the masked bits. When masking is implemented, the output of the pixel modification unit is derived from the masked bits from the destination operand and the unmasked bits which are operated on by the logic function unit. The byte mirror unit horizontally reflects a figure in the bit map via reversing the bit order of data bytes retrieved from the bit map.
摘要翻译：提供像素修改单元，用于在RISC图形处理器中执行各种光栅图形操作。像素修改单元包括逻辑功能单元，掩蔽单元和字节镜单元。逻辑功能单元可以执行源操作数和目标操作数的每个位之间的16种不同逻辑运算中的任何一种。源操作数可以是位图固定数据，而目的地操作数是与要修改的图形图像对应的位图中的像素数据。掩蔽单元可以屏蔽目标操作数的任何或所有位，使得逻辑功能单元不对掩码位进行操作。当实现掩蔽时，从目标操作数的屏蔽位和由逻辑功能单元操作的未屏蔽位导出像素修改单元的输出。字节镜单元通过反转从位图检索的数据字节的位顺序水平地反映位图中的图形。

4. 发明申请

WO1993011499A1 ORTHOGONAL ROTATOR 审中-公开
标题翻译：正交旋转器
公开(公告)号：WO1993011499A1
公开(公告)日：1993-06-10
申请号：PCT/JP1992001558
申请日：1992-11-27
申请人： SEIKO EPSON CORPORATION
发明人： SEIKO EPSON CORPORATION , LENTZ, Derek, J. , YOUNG, Linley, M.
IPC分类号： G06F15/66
CPC分类号： G06T3/606
摘要： A high performance orthogonal rotator for a graphics processor orthogonally rotates pixel regions in a bit map by an angle of 90 DEG or 270 DEG . Optionally, the pixel regions can be vertically mirrored as well as orthogonally rotated. Source data bytes from a source bit map are loaded into columns of a matrix array constructed from parallel registers forming the rows. Orthogonal rotation and vertical mirroring is accomplished by the order in which bytes are loaded from the source bit map and by the order in which bytes are read into a destination bit map. To accomplish a 90 DEG rotation without vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the LSB column and ending with the MSB column. Then, data words are read beginning with the MSW located in the bottom register and ending with the LSW located in the top register. To achieve a 90 DEG rotation with vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the LSB column and ending with the MSB column. Then, data words are read beginning with the LSW in the top register and ending with the MSW in the bottom register. To accomplish a 270 DEG rotation without vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the MSB column and ending with the LSB column. Then, data words are read beginning with the LSW in the top register (108) and ending with the MSW in the bottom register. To effectuate a 270 DEG rotation with vertical mirroring, data bytes are first loaded into the matrix array columns beginning with the MSB column and ending with the LSB column. Then, data words are read beginning with the MSW in the bottom register and ending with the LSW in the top register.
摘要翻译：用于图形处理器的高性能正交旋转器将位图中的像素区域正交地旋转90°或270°的角度。可选地，像素区域可以被垂直镜像以及正交旋转。来自源位图的源数据字节被加载到由形成行的并行寄存器构成的矩阵数组的列中。正交旋转和垂直镜像通过从源位图加载字节的顺序以及将字节读入目标位图的顺序来完成。为了完成没有垂直镜像的90°旋转，首先将数据字节加载到以LSB列开头并以MSB列结尾的矩阵阵列列中。然后，数据字从位于底部寄存器中的MSW开始读取，并以位于顶部寄存器中的LSW结束。要使用垂直镜像实现90°旋转，首先将数据字节加载到以LSB列开头并以MSB列结尾的矩阵阵列列中。然后，数据字从顶部寄存器中的LSW开始读取，并以底部寄存器中的MSW结束。为了在没有垂直镜像的情况下完成270°旋转，首先将数据字节加载到以MSB列开头并以LSB列结尾的矩阵阵列列中。然后，数据字从顶部寄存器（108）中的LSW开始读取，并以底部寄存器中的MSW结束。要使用垂直镜像实现270°旋转，首先将数据字节加载到以MSB列开头并以LSB列结尾的矩阵阵列列中。然后，数据字从底部寄存器中的MSW开始读取，并以顶部寄存器中的LSW结束。

5. 发明公开

EP0547242A1 SINGLE CHIP PAGE PRINTER CONTROLLER 失效
标题翻译： SINGLE-CHIP页式打印机的控制电路。
公开(公告)号：EP0547242A1
公开(公告)日：1993-06-23
申请号：EP92914388.0
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： LENTZ, Derek, J. , WANG, Johannes , DEOSARAN, Trevor , YOUNG, Linley, M. , YAP, Kian-Chin , NGUYEN, Le Trong , MATSUBAYASHI, Makoto Seiko Epson Corporation , LAU, Te-Li
IPC分类号： B41J5 , B41J29 , G06F3 , G06F9 , G06F15 , G06K15 , G06T1
CPC分类号： G06F9/30018 , G06K15/00 , G06K15/02 , G06K2215/0002 , G06K2215/0005 , G06K2215/004 , G06K2215/0054 , G06K2215/0062 , G06K2215/0071 , G06K2215/0082
摘要： Contrôleur d'imprimante page-par-page, comprenant un processeur d'instructions, un processeur vidéo d'imprimante pourvu d'une porte vidéo, une antémémoire d'instructions et de données, un contrôleur de mémoire interconnectant le processeur vidéo et une mémoire externe ainsi que l'antémémoire d'instructions et de données, et un contrôleur d'entrée-sortie interconnectant le contrôleur d'imprimante à un bus d'entrée-sortie. Le processeur vidéo d'imprimante est intégré au contrôleur d'entrée-sortie et à l'interface de mémoire afin d'optimaliser la largeur de bande de la mémoire et de permettre d'obtenir un accès prioritaire à la mémoire. Le processeur d'instruction est connecté à un ordinateur central par l'intermédiaire du bus d'entrée-sortie. Le processeur d'instruction comprend un circuit de modification de pixel, un circuit de rotation orthogonale, et un circuit de création d'image-miroir de bit/d'octet. Le processeur vidéo est connecté avec le processeur d'instructions par l'intermédiaire du bus d'entrée-sortie, et avec la mémoire par l'interface de mémoire. Le processeur vidéo commande aussi une imprimante par l'intermédiaire de la porte vidéo.

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