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1. 发明申请

US20030058016A1 Operation control according to temperature variation in integrated circuit 失效
标题翻译：根据集成电路的温度变化进行运行控制
公开(公告)号：US20030058016A1
公开(公告)日：2003-03-27
申请号：US10245586
申请日：2002-09-18
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： H03K003/037
CPC分类号： G11C7/04 , G11C11/406
摘要： A semiconductor memory device, such as a virtual SRAM, includes a temperature detection module and a temperature characteristic regulation module. The temperature detection module has a temperature sensing element, which includes a specific pn junction area set in a cutoff state out of pn junction areas formed on an identical semiconductor substrate with a memory cell array and outputs a leak current running through the specific pn junction area. The temperature detection module detects a temperature change of the semiconductor memory device in response to the leak current output from the temperature sensing element. The temperature characteristic regulation module regulates a generation period of a refresh timing signal, which is used to determine an execution timing of a refreshing operation in the memory cell array, based on a result of the detection by the temperature detection module. This arrangement of the present invention attains a low-consumption level of electric current equivalent to that of a conventional SRAM.
摘要翻译：诸如虚拟SRAM的半导体存储器件包括温度检测模块和温度特性调节模块。温度检测模块具有温度感测元件，其包括在与存储单元阵列相同的半导体衬底上形成的pn结区域中处于截止状态的特定pn结区域，并输出穿过特定pn结区域的漏电流。温度检测模块响应于从温度感测元件输出的泄漏电流来检测半导体存储器件的温度变化。温度特性调节模块基于温度检测模块的检测结果来调节用于确定存储单元阵列中的刷新操作的执行定时的刷新定时信号的生成周期。本发明的这种布置实现了与常规SRAM相当的低消耗电流水平。

2. 发明申请

US20030012060A1 Technique of controlling noise of power supply in semiconductor memory device 失效
标题翻译：控制半导体存储器件电源噪声的技术
公开(公告)号：US20030012060A1
公开(公告)日：2003-01-16
申请号：US10119841
申请日：2002-04-11
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C029/00
CPC分类号： G11C7/1057 , G11C11/4074 , G11C2207/2227
摘要： A semiconductor memory device includes: at least one memory cell block including multiple dynamic memory cells arrayed in a matrix; a row address decoder and a column address decoder that select a memory cell in the memory cell block, which is specified by an address including a row address and a column address; an output buffer that causes data to be output from the selected memory cell specified by the address; a preset circuit that presets an output level of the output buffer; and a preset control module that controls an operation of the preset circuit. At every time of outputting data from the memory cell selected by the column address decoder, the output level of the output buffer is preset, prior to output of the data from the selected memory cell by means of the output buffer. This arrangement effectively prevents the potential noise in a power source of the semiconductor memory device.
摘要翻译：半导体存储器件包括：至少一个存储单元块，其包括以矩阵形式排列的多个动态存储单元; 行地址解码器和列地址解码器，其选择由包括行地址和列地址的地址指定的存储器单元块中的存储单元; 输出缓冲器，其使得从所述地址指定的所选存储单元输出数据; 预置电路，用于预设输出缓冲器的输出电平; 以及控制预置电路的动作的预设控制模块。在从列地址解码器选择的存储单元输出数据的每一次，在通过输出缓冲器从所选择的存储单元输出数据之前，预先设置输出缓冲器的输出电平。这种布置有效地防止了半导体存储器件的电源中的潜在噪声。

3. 发明申请

US20030081487A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20030081487A1
公开(公告)日：2003-05-01
申请号：US10268782
申请日：2002-10-11
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C007/00
CPC分类号： G11C7/22 , G11C8/18 , G11C11/4076
摘要： The technique of the present invention sets a time period of a level H between a rise and a fall of an ATD signal (that is, a pulse width of the ATD signal) to be not shorter than a preset allowable address skew range and not longer than a time period between a timing of a rise of the ATD signal, at which the refreshing operation starts, and conclusion of the refreshing operation. This arrangement ensures generation of an appropriate ATD signal even when an address skew occurs in an externally given address.
摘要翻译：本发明的技术将ATD信号的上升和下降之间的电平H（即，ATD信号的脉冲宽度）的时间周期设置为不短于预设的可允许地址偏移范围，而不是更长比在更新操作开始的ATD信号的上升定时和刷新操作的结束之间的时间段。即使当外部给定的地址发生地址偏移时，也可以确保生成适当的ATD信号。

4. 发明申请

US20020057607A1 Activation of word lines in semiconductor memory device 失效
标题翻译：激活半导体存储器件中的字线
公开(公告)号：US20020057607A1
公开(公告)日：2002-05-16
申请号：US09976164
申请日：2001-10-15
申请人： Seiko Epson Corporation
发明人： Koichi Mizugaki , Eitaro Otsuka
IPC分类号： G11C007/00
CPC分类号： G11C8/08 , G11C11/406 , G11C11/408 , G11C11/4087
摘要： To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the controller maintains an activated state of a word line without deactivation thereof until the row address changes. In the event of a refresh request when a word line in a certain block is in an activated state, the controller can deactivate the word line, with the proviso that no external access is currently being performed in the block. Where a request for external access to the block is made within a predetermined period after the refresh request, the refresh operation for the block is suspended, and the word line for external access is activated.
摘要翻译：提供一种用于降低与半导体存储器件中的字线激活相关联的功耗的技术。半导体存储器件具有用于控制字线激活的字线激活控制器。在连续的操作周期使用包括相同行地址的多位地址的情况下，控制器保持字线的激活状态而不停止其直到行地址改变。在特定块中的字线处于激活状态时的刷新请求的情况下，控制器可以禁用字线，条件是当前在块中不执行外部访问。在刷新请求之后的预定时段内进行对外部访问的请求的情况下，块的刷新操作被暂停，并且用于外部访问的字线被激活。

5. 发明申请

US20020051398A1 Semiconductor device, method for refreshing the same, system memory, and electronics apparatus 失效
标题翻译：半导体器件，其刷新方法，系统存储器和电子设备
公开(公告)号：US20020051398A1
公开(公告)日：2002-05-02
申请号：US09949672
申请日：2001-09-12
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C007/00
CPC分类号： G11C11/406
摘要： The present invention provides a semiconductor device that includes a memory cell array that can be divided into four blocks. During a period in which data is read or written in one of the blocks, refreshing is conducted in all of the other remaining blocks. Also, in a standby state or in an operation state, refreshing for each of the plurality of blocks is performed with time differences provided therebetween, such that the peak current is lowered.
摘要翻译：本发明提供了一种半导体器件，其包括可分为四个块的存储单元阵列。在其中一个块中读取或写入数据的时段期间，在所有剩余的块中进行刷新。此外，在待机状态或操作状态下，通过其间提供时间差来执行多个块中的每个块的刷新，使得峰值电流降低。

6. 发明申请

US20020051389A1 Activation of word lines in semiconductor memory device 失效
标题翻译：激活半导体存储器件中的字线
公开(公告)号：US20020051389A1
公开(公告)日：2002-05-02
申请号：US09976021
申请日：2001-10-15
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki , Eitaro Otsuka
IPC分类号： G11C029/00
CPC分类号： G11C8/08
摘要： To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller can maintain an the activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles. If a refresh operation is to be performed during a cycle among the consecutive cycles after the initial cycle, the word line activation controller can deactivate the activated word line prior to performing the refresh operation.
摘要翻译：提供一种用于降低与半导体存储器件中的字线激活相关联的功耗的技术。半导体存储器件具有用于控制字线激活的字线激活控制器。在连续操作周期使用包括相同行地址的多位地址的情况下，字线激活控制器可以在连续周期的初始周期期间保持激活的字线的激活状态，而不使其停止直到最终周期连续循环。如果在初始周期之后的连续循环中的循环中执行刷新操作，则字线激活控制器可以在执行刷新操作之前停用激活的字线。

7. 发明申请

US20020049884A1 Semiconductor device, refreshing method thereof, memory system, and electronic instrument 失效
标题翻译：半导体器件，刷新方法，存储器系统和电子仪器
公开(公告)号：US20020049884A1
公开(公告)日：2002-04-25
申请号：US09971914
申请日：2001-10-09
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G06F013/00
CPC分类号： G11C11/40622 , G11C11/406
摘要： A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for the other blocks. An RF address controller 120 has a function of making logic of a signal RFA18 and a signal RFA19 among refresh address signals RFA8 to RFA19 constant so that only part of each block of the blocks A to D is refreshed in a power saving state.
摘要翻译：一种刷新诸如VSRAM的半导体器件的方法。半导体器件1的存储单元阵列20被划分为由块A，块B，块C和块D组成的四个块。在对其中一个块进行数据读取或写入操作的时段期间，刷新对其他块执行。 RF地址控制器120具有在刷新地址信号RFA8至RFA19中使信号RFA18和信号RFA19的逻辑恒定的功能，使得块A至D的每个块的仅一部分在省电状态下被刷新。

8. 发明申请

US20020048208A1 Semiconductor device, refreshing method thereof, memory system, and electronic instrument 失效
标题翻译：半导体器件，刷新方法，存储器系统和电子仪器
公开(公告)号：US20020048208A1
公开(公告)日：2002-04-25
申请号：US09972053
申请日：2001-10-09
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C007/00 , G11C008/00 , G11C005/00
CPC分类号： G11C11/406 , G11C8/12 , G11C8/18
摘要： A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for all the remaining blocks. A refresh cycle in a power saving state is caused to be longer than a refresh cycle in an operating state.
摘要翻译：一种刷新诸如VSRAM的半导体器件的方法。半导体器件1的存储单元阵列20被划分为由块A，块B，块C和块D组成的四个块。在对其中一个块进行数据读取或写入操作的时段期间，刷新对所有剩余的块执行。导致省电状态的刷新周期比操作状态下的刷新周期长。

9. 发明申请

US20020027821A1 Refresh control for semiconductor memory device 失效
公开(公告)号：US20020027821A1
公开(公告)日：2002-03-07
申请号：US09935694
申请日：2001-08-24
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C007/00
CPC分类号： G11C11/406 , G11C7/1045
摘要： In the operation cycle, memory chip 200 initiates a refresh operation in sync with an ATD signal indicating change of address after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of the ATD signal.

10. 发明申请

US20020027820A1 Refresh control for semiconductor memory device 失效
标题翻译：半导体存储器件的刷新控制
公开(公告)号：US20020027820A1
公开(公告)日：2002-03-07
申请号：US09935693
申请日：2001-08-24
申请人： SEIKO EPSON CORPORATION
发明人： Koichi Mizugaki
IPC分类号： G11C007/12
CPC分类号： G11C7/1045 , G11C7/1072 , G11C11/406
摘要： In the operation cycle, memory chip 200 initiates a refresh operation in synchronism with an external clock signal CLK after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of a clock signal CLK.
摘要翻译：在操作周期中，在刷新定时信号RFTM被发出之后，存储芯片200与外部时钟信号CLK同步地启动刷新操作。在打盹模式（低功耗模式）中，响应于产生刷新定时信号RFTM而启动刷新操作，而与时钟信号CLK无关。

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