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1. 发明授权

EP1260908B1 Data transfer control device, electronic equipment, and data transfer control method 有权
标题翻译：数据控制系统，用于传输控制的电子设备和方法
公开(公告)号：EP1260908B1
公开(公告)日：2005-08-03
申请号：EP02010402.2
申请日：2002-05-08
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki , Ishida, Takuya
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/385 , G06F13/28 , G06F13/4027

2. 发明公开

EP1202151A3 Data transfer control device and electronic equipment 审中-公开
标题翻译： Geren公司的Datensteueranlage und elektronischesGerät
公开(公告)号：EP1202151A3
公开(公告)日：2003-05-21
申请号：EP01125404.2
申请日：2001-10-31
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki
IPC分类号： G06F1/08 , G06F1/06
CPC分类号： H03L7/07 , G06F1/06 , H03L7/0995 , H03L7/18
摘要： The objective is to provide a data transfer control device and electronic equipment that make it possible to switch the frequency of a generated clock dynamically, without causing any operating errors. The data transfer control device includes a clock generation circuit which generates clocks CLKH and CLKF and a clock control circuit which generates a system clock SYCLK based on CLKH and CLKF. The autonomous operation of a PLL60M that generates CLKF is enabled before the autonomous operation of a PLL480M that generates CLKH is disabled, and the generation source of SYCLK is switched from CLKH to CLKF after the autonomous operation of the PLL60M has stabilized. On condition that CLKH becomes "0", SYCLK is set to "0" for a given period only; and on condition that CLKF becomes "0", SYCLK is generated based on CLKF. When the mode switches from HS mode FS mode under USB 2.0, the operation of the PLL480M is disabled, reducing the power consumption.
摘要翻译：目的是提供一种数据传输控制装置和电子设备，使得可以动态地切换所产生的时钟的频率，而不引起任何操作错误。数据传输控制装置包括产生时钟CLKH和CLKF的时钟产生电路以及基于CLKH和CLKF产生系统时钟SYCLK的时钟控制电路。在产生CLKH的PLL480M的自主操作被禁用之前，产生CLKF的PLL60M的自主操作被使能，并且在PLL60M的自动操作已经稳定之后，SYCLK的发生源从CLKH切换到CLKF。在CLKH变为“0”的情况下，仅在给定时间内将SYCLK设置为“0” 并且在CLKF变为“0”的情况下，基于CLKF生成SYCLK。当USB 2.0模式从HS模式FS模式切换时，PLL480M的操作被禁用，从而降低功耗。

3. 发明公开

EP1258798A2 Data transfer control device, electronic equipment, and data transfer control method 有权
标题翻译：数据转换器，电动机和数据转换器
公开(公告)号：EP1258798A2
公开(公告)日：2002-11-20
申请号：EP02010722.3
申请日：2002-05-14
申请人： SEIKO EPSON CORPORATION
发明人： Ishida, Takuya , Kamihara, Yoshiyuki
IPC分类号： G06F5/06
CPC分类号： G06F5/10
摘要： A buffer is provided which includes an EP2 area 14 (a data storage area set to FIFO) and a CSW area 16 (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EP2. When a phase has switched from a USB data phase (data transport) to a status phase (status transport), the information read area is switched from the EP2 area 14 to the CSW area 16, and IN data to be transferred from the end point EP2 to a host is read from the CSW area 16. A CSW0 area for success status and a CSW1 area for non-success status are provided, and a status block packet in which is set either success or non-success default information is previously written therein.
摘要翻译：提供了一种缓冲器，其包括EP2区域14（设置为FIFO的数据存储区域）和CSW区域16（随机可访问状态存储区域），当数据和CSW被分配为要通过一个端点EP2传送的信息时。当相位从USB数据相位（数据传输）切换到状态阶段（状态传输）时，信息读取区域从EP2区域14切换到CSW区域16，并且从端点传送IN数据从CSW区域16读取到主机的EP2。提供用于成功状态的CSW0区域和用于非成功状态的CSW1区域，并且其中设置成功或非成功默认信息的状态块分组被预先写入在其中。

4. 发明公开

EP1199837A2 Sampling clock generation circuit, data transfer control device, and electronic equipment 有权
标题翻译：电路，用于产生用于数据传送装置的采样时钟;和电子设备
公开(公告)号：EP1199837A2
公开(公告)日：2002-04-24
申请号：EP01124703.8
申请日：2001-10-16
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki
IPC分类号： H04L7/033 , G06F13/38
CPC分类号： G06F1/06 , H03K3/0322 , H03L7/0996 , H03L7/18 , H04L7/0337
摘要： A sampling clock generation circuit and a data transfer control device make it possible to ensure a set-up time and the like during sampling, while maintaining a high frequency. A sampling clock generation circuit comprises an edge detection circuit detecting between which two edges an edge of data DIN (data to be transferred in USB 2.0 HS mode) is located, the two edges are among edges of clocks CLK0 to CLK4 that have the same frequency but mutually different phases, and a clock selection circuit, which selects one of CLK0 to CLK4 based on this edge detection information and outputs the thus-selected clock as a sampling clock SCLK. When the set-up time of a D flip-flop of the edge detection circuit is TS, the hold time is TH, and the period of the clock is T, N which is the number of a multi-phase clock is given by: N ≦ [T/(TS + TH)] (where [X] is the maximum integer that does not exceed X). The clock that has an edge that is shifted by a set number M from an edge of the data DIN is selected as SCLK.
摘要翻译：采样时钟生成电路和数据传输控制装置使得能够确保一组时间和采样期间等，同时维持高的频率。采样时钟生成电路在数据DIN的边缘两个边缘之间检测边沿检测电路的方法包括：（数据以USB要传输2.0 HS模式）的位置，所述两个边缘到CLK4时钟CLK0的边缘中thathave相同的频率但相互不同的相位，和时钟选择电路，其选择基于该边缘检测信息到CLK4 CLK0的一个和所选择的时钟由此作为一种采样时钟SCLK输出。当边缘检测电路的D触发器的设置时间是TS，保持时间是TH，并且时钟的周期是T，N的所有这是一个多相位时钟的数量由下式给出： ñ

5. 发明公开

EP1199837A3 Sampling clock generation circuit, data transfer control device, and electronic equipment 有权
标题翻译：电路，用于产生用于数据传送装置的采样时钟;和电子设备
公开(公告)号：EP1199837A3
公开(公告)日：2003-07-02
申请号：EP01124703.8
申请日：2001-10-16
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki
IPC分类号： H04L7/033 , G06F13/38
CPC分类号： G06F1/06 , H03K3/0322 , H03L7/0996 , H03L7/18 , H04L7/0337
摘要： A sampling clock generation circuit and a data transfer control device make it possible to ensure a set-up time and the like during sampling, while maintaining a high frequency. A sampling clock generation circuit comprises an edge detection circuit detecting between which two edges an edge of data DIN (data to be transferred in USB 2.0 HS mode) is located, the two edges are among edges of clocks CLK0 to CLK4 that have the same frequency but mutually different phases, and a clock selection circuit, which selects one of CLK0 to CLK4 based on this edge detection information and outputs the thus-selected clock as a sampling clock SCLK. When the set-up time of a D flip-flop of the edge detection circuit is TS, the hold time is TH, and the period of the clock is T, N which is the number of a multi-phase clock is given by: N ≦ [T/(TS + TH)] (where [X] is the maximum integer that does not exceed X). The clock that has an edge that is shifted by a set number M from an edge of the data DIN is selected as SCLK.

6. 发明公开

EP1258798A3 Data transfer control device, electronic equipment, and data transfer control method 有权
标题翻译：数据传输控制系统，电子设备和数据传输控制方法
公开(公告)号：EP1258798A3
公开(公告)日：2003-05-21
申请号：EP02010722.3
申请日：2002-05-14
申请人： SEIKO EPSON CORPORATION
发明人： Ishida, Takuya , Kamihara, Yoshiyuki
IPC分类号： G06F5/06 , G06F13/38 , G06F13/42
CPC分类号： G06F5/10
摘要： A buffer is provided which includes an EP2 area 14 (a data storage area set to FIFO) and a CSW area 16 (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EP2. When a phase has switched from a USB data phase (data transport) to a status phase (status transport), the information read area is switched from the EP2 area 14 to the CSW area 16, and IN data to be transferred from the end point EP2 to a host is read from the CSW area 16. A CSW0 area for success status and a CSW1 area for non-success status are provided, and a status block packet in which is set either success or non-success default information is previously written therein.

7. 发明公开

EP1260908A2 Data transfer control device, electronic equipment, and data transfer control method 有权
标题翻译：数据控制系统，用于传输控制的电子设备和方法
公开(公告)号：EP1260908A2
公开(公告)日：2002-11-27
申请号：EP02010402.2
申请日：2002-05-08
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki , Ishida, Takuya
IPC分类号： G06F13/12 , G06F13/42
CPC分类号： G06F13/385 , G06F13/28 , G06F13/4027
摘要： A data transfer control device using USB (a first bus), the end of a data phase (data transport: transfer of all the data) during an OUT transaction is determined on condition that data transmission (DMA transfer) through EBUS (a second bus) has ended, and the end of a data phase during an IN transaction is determined on condition that data reception through EBUS has ended and also an Empty signal has gone active, indicating that a data storage area has become empty. A counter that counts the data size is provided on the EBUS side. If data reception through EBUS ends and the size of data remaining in the data storage area is less than the maximum packet size, a short packet in the data storage area is transmitted automatically through USB and an interrupt is used to notify the firmware of the presence of the short packet.

8. 发明授权

EP1199837B1 Sampling clock generation circuit, data transfer control device, and electronic equipment 有权
标题翻译：电路，用于产生用于数据传送装置的采样时钟;和电子设备
公开(公告)号：EP1199837B1
公开(公告)日：2006-12-20
申请号：EP01124703.8
申请日：2001-10-16
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki
IPC分类号： H04L7/033 , G06F13/38
CPC分类号： G06F1/06 , H03K3/0322 , H03L7/0996 , H03L7/18 , H04L7/0337

9. 发明公开

EP1202163A3 Serial/parallel conversion circuit, data transfer control device, and electronic equipment 审中-公开
标题翻译：串行到并行的数据传输控制转换装置，和电子设备
公开(公告)号：EP1202163A3
公开(公告)日：2004-09-08
申请号：EP01125159.2
申请日：2001-10-23
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki , Ishida, Takuya
IPC分类号： G06F5/06 , H03M9/00
CPC分类号： G06F5/06 , H03M9/00 , H04J3/0685
摘要： The present invention provides a serial/parallel conversion circuit that has both a serial/parallel conversion function and a buffer function for absorbing clock frequency differences, together with a data transfer control device and electronic equipment. The serial/parallel conversion circuit (elasticity buffer) comprises a data holding register which holds serial data DIN that is input based on a CLK1 clock (480 MHz) in USB 2.0 HS mode; a determination circuit which determines whether or not held data is valid, by unit of a data cell; and a selector which outputs from the data holding register the data of data cells that have been determined to be valid, based on a CLK2 clock (60 MHz) having a frequency lower than that of CLK1. A data cell in which data of the first bit has been determined to be valid is deemed to be valid in the next CLK2 clock cycle. The determination of whether or not data cells are valid is done in each clock cycle of CLK2, and the output of data in a data cell that is determined not to be valid is made to wait for one clockcycle. Awrite pulse signal is generated and the data holding register and data status register are operated thereby.

10. 发明公开

EP1202163A2 Serial/parallel conversion circuit, data transfer control device, and electronic equipment 审中-公开
标题翻译： Seriell-Parallel-Umsetzer，GerätzurDatenübertragungssteuerung，und elektronische Vorrichtung
公开(公告)号：EP1202163A2
公开(公告)日：2002-05-02
申请号：EP01125159.2
申请日：2001-10-23
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki , Ishida, Takuya
IPC分类号： G06F5/06
CPC分类号： G06F5/06 , H03M9/00 , H04J3/0685
摘要： The present invention provides a serial/parallel conversion circuit that has both a serial/parallel conversion function and a buffer function for absorbing clock frequency differences, together with a data transfer control device and electronic equipment. The serial/parallel conversion circuit (elasticity buffer) comprises a data holding register which holds serial data DIN that is input based on a CLK1 clock (480 MHz) in USB 2.0 HS mode; a determination circuit which determines whether or not held data is valid, by unit of a data cell; and a selector which outputs from the data holding register the data of data cells that have been determined to be valid, based on a CLK2 clock (60 MHz) having a frequency lower than that of CLK1. A data cell in which data of the first bit has been determined to be valid is deemed to be valid in the next CLK2 clock cycle. The determination of whether or not data cells are valid is done in each clock cycle of CLK2, and the output of data in a data cell that is determined not to be valid is made to wait for one clockcycle. Awrite pulse signal is generated and the data holding register and data status register are operated thereby.
摘要翻译：本发明提供一种串行/并行转换电路，其具有串行/并行转换功能和用于吸收时钟频率差的缓冲功能，以及数据传输控制装置和电子设备。串行/并行转换电路（弹性缓冲器）包括一个数据保持寄存器，其保存在USB 2.0 HS模式下基于CLK1时钟（480MHz）输入的串行数据DIN; 确定电路，其以数据单元为单位确定保持数据是否有效; 以及选择器，其基于具有低于CLK1的频率的CLK2时钟（60MHz）从数据保持寄存器输出已被确定为有效的数据的数据。其中第一位的数据被确定为有效的数据单元被认为在下一个CLK2时钟周期中有效。在CLK2的每个时钟周期中确定数据单元是否有效，并且确定被确定为不有效的数据单元中的数据的输出等待一个时钟周期。产生写入脉冲信号，由此操作数据保持寄存器和数据状态寄存器。

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