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1. 发明申请

WO9320507A3 CISC TO RISC INSTRUCTION TRANSLATION ALIGNMENT AND DECODING 审中-公开
标题翻译： CISC指令翻译对齐和解码
公开(公告)号：WO9320507A3
公开(公告)日：1994-01-06
申请号：PCT/JP9300417
申请日：1993-03-30
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
CPC分类号： G06F9/30101 , C10G1/00 , C10G17/02 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

2. 发明专利

DE69333630T2 未知
公开(公告)号：DE69333630T2
公开(公告)日：2005-09-22
申请号：DE69333630
申请日：1993-03-30
申请人： SEIKO EPSON CORP
发明人： COON BRETT , NGUYEN LE TRONG , MIYAYAMA YOSHIYUKI , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

3. 发明专利

DE69329644T2 未知
公开(公告)号：DE69329644T2
公开(公告)日：2001-03-01
申请号：DE69329644
申请日：1993-03-30
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

4. 发明专利

DE69333630D1 未知
公开(公告)号：DE69333630D1
公开(公告)日：2004-10-21
申请号：DE69333630
申请日：1993-03-30
申请人： SEIKO EPSON CORP
发明人： COON BRETT , NGUYEN LE TRONG , MIYAYAMA YOSHIYUKI , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

5. 发明专利

DE69329644D1 未知
公开(公告)号：DE69329644D1
公开(公告)日：2000-12-14
申请号：DE69329644
申请日：1993-03-30
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

6. 发明专利

JP2000215054A ALIGNMENT SYSTEM FOR COMPOSITE INSTRUCTION STREAM 失效
公开(公告)号：JP2000215054A
公开(公告)日：2000-08-04
申请号：JP2000007265
申请日：2000-01-17
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： G06F9/38 , G06F9/30 , G06F9/305 , G06F9/315 , G06F9/32 , G06F9/455
摘要： PROBLEM TO BE SOLVED: To execute a composite instruction on the hardware of a reduced instruction set computer by receiving aligned composite instruction bytes from an array latch and determining the number of prefix bytes included in the beginning of the aligned composite instruction bytes. SOLUTION: Four decoders 1002 to 1008 each determine whether or not a prefix is present by checking one of starting four bytes (1010 to 1013). The prefix bytes are able to follow operation code bytes, so a logic gate 1010 is used to output a result showing the total number of prefixes before the starting operation code bytes. Namely, the prefix following the operation code applies to only the operation code of a next instruction. Namely, the total prefix number is 1 when a 1st byte (position) is a prefix and no prefix is present at a 2nd position.

7. 发明专利

JP2000215051A CONVERSION SYSTEM FOR INSTRUCTION STREAM 失效
公开(公告)号：JP2000215051A
公开(公告)日：2000-08-04
申请号：JP2000007262
申请日：2000-01-17
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
摘要： PROBLEM TO BE SOLVED: To execute a composite instruction on the hardware of a reduced instruction set computer by allowing a selector to integrate subsets into a final bucket having the maximum capacity of a specific number of native instructions and outputting the subsets of native instructions of the final bucket on a host processor. SOLUTION: An IAU is divided into a main data bus 302 and a predecoder 304. Instructions are shifted or extracted on the main data bus 302 and determination of the length and control over the data bus are processed by the predecoder 304. Then the selector integrates subsets of at least two groups of native instructions into the final bucket having the maximum capacity of a specific number of native instructions to make it possible to output the subsets of the native instructions of the final bucket on the host processor. Further, two intermediate buckets are able to up to four native instructions at a time.

8. 发明专利

JP2000215052A COMPUTER SYSTEM 失效
公开(公告)号：JP2000215052A
公开(公告)日：2000-08-04
申请号：JP2000007263
申请日：2000-01-17
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： G06F9/38 , G06F9/30 , G06F9/305 , G06F9/315 , G06F9/32 , G06F9/455
摘要： PROBLEM TO BE SOLVED: To execute a composite instruction on the hardware of a reduced instruction set computer by storing a group of native instructions in an intermediate bucket and integrating them into a final bucket, and outputting subsets of native instructions of the final bucket. SOLUTION: An IAU is divided into a main data base 302 and a predecoder 304. Instructions are shifted or extracted on the main data bus 302 and determination of the length and control over the data bus are processed by the predecoder 304. An IFU updates the instruction information of an advance buffer request line 308 on it at a request from the IAU. The subsets of two groups are integrated into the final bucket having the maximum capacity of a specific number of native instructions to make it possible to output the subsets of the native instructions of the final bucket on a host processor. The specific number of native instructions are four native instructions.

9. 发明专利

JP2000215047A CONVERSION SYSTEM FOR INSTRUCTION STREAM 失效
公开(公告)号：JP2000215047A
公开(公告)日：2000-08-04
申请号：JP2000007258
申请日：2000-01-17
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： G06F9/38 , G06F9/30 , G06F9/305 , G06F9/315 , G06F9/32 , G06F9/455
摘要： PROBLEM TO BE SOLVED: To execute a composite instruction on the hardware of a reduced instruction set computer by storing up to a specific number of native instructions in an intermediate buffer and allowing a final buffer to have the maximum capacity of a specific number of native instructions. SOLUTION: An IAU is divided into a main data bus 302 and a predecoder 304. Instructions are shifted or extracted on the main data bus 302 and determination of the length and control over the data bus are processed by the predecoder 304. Then respective groups of native instructions include at least one native instruction and the number of native instructions which are included is not more a specific number; and two intermediate buffers are able to store up to a specific number of native instructions and the final buffer has the maximum capacity of a specific number of native instructions. At least one of the two intermediate buffers is able to store up to four native instructions at a time.

10. 发明专利

JP2000215053A CONVERTING METHOD FOR INSTRUCTION STREAM 失效
公开(公告)号：JP2000215053A
公开(公告)日：2000-08-04
申请号：JP2000007264
申请日：2000-01-17
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： G06F9/38 , G06F9/30 , G06F9/305 , G06F9/315 , G06F9/32 , G06F9/455
摘要： PROBLEM TO BE SOLVED: To execute a composite instruction on the hardware of a reduced instruction set computer by integrating subsets of groups of native instructions into a final bucket and outputting the subsets of the native instructions of the final bucket on a host processor. SOLUTION: A main instruction buffer(MBUF) 204, an emulation instruction buffer(EBUF) 202, and a target instruction buffer(TBUF) 206 are provided. An instruction prefetch buffer loads a 128-bit (16 bytes) instruction stream from an instruction cache in a single cycle. Then subsets of at least two groups of native instructions are integrated into the final bucket to output the subsets of the native instructions of the final bucket having the maximum capacity of a specific number of native instructions on the host processor. This intermediate bucket is able to store up to four native instructions.

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