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1. 发明申请

WO2008089153A3 METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES 审中-公开
标题翻译：使用辅助层形成高密度半导体器件的间隔图案的方法
公开(公告)号：WO2008089153A3
公开(公告)日：2008-09-12
申请号：PCT/US2008051017
申请日：2008-01-14
申请人： SANDISK CORP , KAI JAMES , METAMIS GEORGE , PHAM TUAN DUC , HIGASHITANI MASAAKI , ORIMOTO TAKASHI
发明人： KAI JAMES , METAMIS GEORGE , PHAM TUAN DUC , HIGASHITANI MASAAKI , ORIMOTO TAKASHI
IPC分类号： H01L21/033 , H01L21/28 , H01L21/308 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/28273 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L27/115 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers (620-634) are formed that serve as a mask, for etching one or more layers (604) beneath the spacers. An etch stop pad layer (608) having a material composition substantially similar to the spacer material is provided between a dielectric layer (606) and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成用作掩模的隔板（620-634），用于蚀刻间隔物下面的一个或多个层（604）。具有与间隔物材料基本相似的材料组成的蚀刻停止衬垫层（608）设置在电介质层（606）和绝缘牺牲层（例如氮化硅）之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

2. 发明申请

WO2008122012A3 INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
标题翻译：集成的非易失性存储器和外围电路制造
公开(公告)号：WO2008122012A3
公开(公告)日：2008-11-20
申请号：PCT/US2008059035
申请日：2008-04-01
申请人： SANDISK CORP , KAI JAMES , PHAM TUAN , HIGASHITANI MASAAKI , MATAMIS GEORGE , ORIMOTO TAKASHI
发明人： KAI JAMES , PHAM TUAN , HIGASHITANI MASAAKI , MATAMIS GEORGE , ORIMOTO TAKASHI
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory (480) and peripheral circuitry (490) fabrication processes are provided. Sets of charge storage regions (406, 408), such as NAND strings including multiple non- volatile storage elements, are formed over a semiconductor substrate (402) using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer (404) is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates (416, 418) for the charge storage regions and the gate regions (434) of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions (444, 448) of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供了非易失性存储器和集成存储器（480）和外围电路（490）制造工艺。使用诸如第一多晶硅层的电荷存储材料层，在半导体衬底（402）上形成电荷存储区（406,408），诸如包括多个非易失性存储元件的NAND串。中间电介质层（404）设置在电荷存储区域上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于电荷存储区域的控制栅极（416,418）和用于存储器组的选择晶体管的栅极区域（434）元素。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域（444,448）可以由形成存储器阵列的控制栅极的层形成。

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