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1. 发明申请

WO2009005614A3 3D R/W CELL WITH DIODE AND RESISTIVE SEMICONDUCTOR ELEMENT AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有二极管和电阻半导体元件的3D R / W单元及其制造方法
公开(公告)号：WO2009005614A3
公开(公告)日：2009-03-26
申请号：PCT/US2008007758
申请日：2008-06-23
申请人： SANDISK 3D LLC , KUMAR TANMAY , PETTI CHRISTOPHER J
发明人： KUMAR TANMAY , PETTI CHRISTOPHER J
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0002 , G11C2213/33 , G11C2213/72 , H01L27/24
摘要： A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read / write switching element.
摘要翻译：非易失性存储器件包括半导体二极管操作元件和半导体读/写开关元件。

2. 发明申请

WO2006121837A3 NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL 审中-公开
标题翻译：包含二极管和电阻切换材料的非易失性存储单元
公开(公告)号：WO2006121837A3
公开(公告)日：2007-01-04
申请号：PCT/US2006017376
申请日：2006-05-05
申请人： SANDISK 3D LLC , HERNER S BRAD , KUMAR TANMAY , PETTI CHRISTOPHER J
发明人： HERNER S BRAD , KUMAR TANMAY , PETTI CHRISTOPHER J
IPC分类号： G11C13/02 , G11C16/02 , H01L23/525 , H01L27/102 , H01L27/24
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and Al x N y . In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选地为金属氧化物或氮化物，例如Ni x O y O y，铌，铌，铌，钇，铌，SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB 其中，O x Y y O y，Y x O y，Y O x O x，X x O，O x O，X x O， y，x，x，y，y，x，y，x，y，x， / SUB＆gt; Y＆gt;和＆lt; N＆gt; N＆lt; / SUB＆gt;。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

3. 发明申请

WO2008016420A3 MULTI-USE MEMORY CELL AND MEMORY ARRAY AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：多用途存储器单元和存储器阵列及其使用方法
公开(公告)号：WO2008016420A3
公开(公告)日：2008-03-27
申请号：PCT/US2007013770
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , KUMAR TANMAY
发明人： SCHEUERLEIN ROY E , KUMAR TANMAY
IPC分类号： G11C17/14 , G11C11/56 , G11C13/00
CPC分类号： G11C11/56 , G11C13/00 , G11C17/06 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/027 , G11C29/028 , G11C2211/5641
摘要： A multi-use memory cell and memory array and a method for use therewith are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.
摘要翻译：公开了一种多用途存储单元和存储器阵列及其使用方法。在一个优选实施例中，存储器单元可操作为一次性可编程存储器单元或可重写存储单元。存储单元包括存储元件，其包括可配置为至少三种电阻率状态之一的半导体材料，其中当存储器单元作为一次可编程存储单元操作时，第一电阻率状态用于表示存储单元的数据状态但是当存储器单元作为可重写存储单元时不起作用。还公开了具有这种存储单元的存储器阵列。在另一个优选实施例中，提供了一种包括可切换电阻材料的存储单元，其中存储单元可在第一模式中操作，其中存储单元用正向偏置和第二模式编程，其中存储单元用反向偏差。

4. 发明申请

WO2008008171A2 BANDGAP ENGINEERED CHARGE STORAGE LAYER FOR 3D TFT 审中-公开
标题翻译：用于3D TFT的BANDGAP工程充电储存层
公开(公告)号：WO2008008171A2
公开(公告)日：2008-01-17
申请号：PCT/US2007014732
申请日：2007-06-26
申请人： SANDISK 3D LLC , KUMAR TANMAY
发明人： KUMAR TANMAY
IPC分类号： H01L29/792
CPC分类号： H01L29/792
摘要： One SONOS-type device contains (a) a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric, and (b) a semiconductor channel region that contains polysilicon. Another SONOS-type device contains a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric. The device is located in a monolithic three dimensional memory array. Yet another SONOS-type device contains a charge storage dielectric that includes a band engineered layer that has a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric and also includes at least one of: (a) a first dielectric layer located between the tunneling dielectric and the band engineered layer, and (b) a second dielectric layer located between the blocking dielectric and the band engineered layer.
摘要翻译：一种SONOS型器件包含（a）电荷存储电介质，其包括带状工程化层，其具有面对阻挡电介质和隧道电介质之一的较宽的带隙，而不是面对阻挡电介质和隧道电介质中的另一个，并且（ b）包含多晶硅的半导体沟道区。另一个SONOS型器件包含电荷存储电介质，其包括带状工程层，其具有面向阻挡电介质和隧道电介质之一的较宽的带隙，而不是面对阻挡电介质和隧道电介质中的另一个。该器件位于单片三维存储器阵列中。另一种SONOS型器件包含电荷存储电介质，其包括带状工程化层，其具有面向隔离电介质和隧道电介质之一的宽带隙，而不是面对阻挡电介质和隧道电介质中的另一个，并且还包括至少以下之一：（a）位于隧道电介质和带工程化层之间的第一介电层，和（b）位于阻挡电介质和带工程化层之间的第二电介质层。

5. 发明申请

WO2007058845A3 VERTICAL DIODE DOPED WITH ANTIMONY TO AVOID OR LIMIT DOPANT DIFFUSION 审中-公开
标题翻译：垂直二极管掺杂锑以避免或限制掺杂物的扩散
公开(公告)号：WO2007058845A3
公开(公告)日：2007-07-12
申请号：PCT/US2006043482
申请日：2006-11-08
申请人： SANDISK 3D LLC , KUMAR TANMAY , HERNER S BRAD
发明人： KUMAR TANMAY , HERNER S BRAD
IPC分类号： H01L29/861 , H01L21/329 , H01L21/84 , H01L27/102 , H01L27/12 , H01L29/167 , H01L29/868
CPC分类号： H01L27/1021 , H01L29/167 , H01L29/861
摘要： Use of antimony as an n-type conductivity-enhancing dopant in semiconductor structures having a vertical dopant profile is described. Dopants tend to diffuse, and steep dopant gradients can be difficult to maintain. Specifically, when a silicon layer is doped with phosphorus or arsenic, both n-type dopants, dopant atoms tend to seek the surface as undoped silicon is deposited on top of the n- doped layer, rising through the undoped silicon during deposition. Antimony does not have this tendency, and also diffuses more slowly than either phosphorus or arsenic, and this is advantageously used to dope such structures.
摘要翻译：描述了在具有垂直掺杂剂分布的半导体结构中使用锑作为n型导电增强掺杂剂。掺杂剂倾向于扩散，并且陡峭的掺杂剂梯度可能难以维持。具体而言，当硅层掺杂有磷或砷时，n型掺杂剂，掺杂剂原子倾向于寻找表面，因为未掺杂的硅被沉积在n掺杂层的顶部上，在沉积期间通过未掺杂的硅上升。锑不具有这种倾向，并且也比磷或砷更慢地扩散，并且这有利于用于掺杂这种结构。

6. 发明申请

WO2008008171A8 BANDGAP ENGINEERED CHARGE STORAGE LAYER FOR 3D TFT 审中-公开
标题翻译：用于3D TFT的BANDGAP工程充电储存层
公开(公告)号：WO2008008171A8
公开(公告)日：2009-03-26
申请号：PCT/US2007014732
申请日：2007-06-26
申请人： SANDISK 3D LLC , KUMAR TANMAY
发明人： KUMAR TANMAY
IPC分类号： H01L27/108
CPC分类号： H01L29/792
摘要： One SONOS-type device contains (a) a charge storage dielectric including a band engineered layer having a wider bandgap facing one of a blocking dielectric and a tunneling dielectric than facing the other one of the blocking dielectric and the tunneling dielectric, and (b) a semiconductor channel region containing polysilicon The device may be located in a monolithic three dimensional memory array The SONOS-type device may also include at least one of (a) a first dielectric layer located between the tunneling dielectric and the band engineered layer, and (b) a second dielectric layer located between the blocking dielectric and the band engineered layer.
摘要翻译：一种SONOS型器件包含（a）包含带状工程层的电荷存储电介质，所述带工程层具有相对于阻挡电介质和隧道电介质中的另一个具有阻挡电介质和隧道电介质的较宽带隙，以及（b）包含多晶硅的半导体通道区域该器件可以位于单片三维存储器阵列中SONOS型器件还可以包括以下中的至少一个：（a）位于隧道电介质和带工程化层之间的第一电介质层和（ b）位于阻挡电介质和带工程化层之间的第二电介质层。

7. 发明申请

WO2009005706A3 METHOD TO FORM A REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTIVITY-SWITCHING GROWN OXIDE 审中-公开
标题翻译：形成包含二极管和电阻开关氧化物的可重复存储单元的方法
公开(公告)号：WO2009005706A3
公开(公告)日：2009-03-19
申请号：PCT/US2008007992
申请日：2008-06-27
申请人： SANDISK 3D LLC , KUMAR TANMAY
发明人： KUMAR TANMAY
IPC分类号： H01L27/10 , G11C11/40 , H01L27/02
CPC分类号： H01L27/1021 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C2213/33 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1633
摘要： A method is described to form a rewriteable memory cell including a diode and an oxide layer, wherein the resistivity of the oxide layer can be reversibly switched. In preferred embodiments, the oxide layer is a grown oxide. The diode is preferably formed of polysilicon which has been crystallized in contact with a silicide which has a close lattice match to silicon. The silicide provides a crystallization template such that the polysilicon is large- grained with few defects, and thus relatively low- resistivity. In preferred embodiments, a monolithic three dimensional memory array can be formed, in which multiple memory levels of such rewriteable memory cells are monolithically formed vertically stacked above a substrate.
摘要翻译：描述了形成包括二极管和氧化物层的可重写存储单元的方法，其中可以可逆地切换氧化物层的电阻率。在优选的实施方案中，氧化物层是生长的氧化物。二极管优选由多晶硅形成，其已经与硅晶体匹配的硅化物接触结晶。硅化物提供结晶模板，使得多晶硅具有很少的缺陷，因此具有相对低的电阻率。在优选实施例中，可以形成单片三维存储器阵列，其中这种可重写存储器单元的多个存储器级别被垂直地堆叠在衬底上方堆叠形成。

8. 发明申请

WO2009045920A3 VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有较低编程电压的基于垂直二极管的存储器单元及其形成方法
公开(公告)号：WO2009045920A3
公开(公告)日：2009-06-11
申请号：PCT/US2008077960
申请日：2008-09-26
申请人： SANDISK 3D LLC , HERNER S BRAD , KUMAR TANMAY
发明人： HERNER S BRAD , KUMAR TANMAY
IPC分类号： H01L27/115
CPC分类号： H01L27/1021 , G11C17/16 , H01L23/5252 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a suicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of suicide, silicide- germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.
摘要翻译：在第一方面，提供了一种用于形成非易失性存储器单元的方法。该方法包括（1）形成包括（a）第一金属层的金属 - 绝缘体 - 金属（MIM）反熔丝堆叠; （b）在第一金属层上方形成的二氧化硅，氮氧化物或氮化硅反熔丝层; 和（c）在反熔丝层上方形成的第二金属层。该方法还包括（2）在MIM堆叠之上形成连续的p-i-n二极管，连续的p-i-n二极管包括沉积的半导体材料; （3）形成与沉积的半导体材料接触的硅化物，硅化物 - 锗化物或锗化物层; （4）使沉积的半导体材料与硅化物，硅化物 - 锗化物或锗化物层接触结晶。存储器单元包括连续的p-i-n二极管和MIM堆栈。其他方面提供。

9. 发明申请

WO2009002476A3 NONVOLATILE MEMORY DEVICE CONTAINING A CARBON- OR NITROGEN-DOPED DIODE AND METHODS OF MAKING ANDOPERATING THE SAME 审中-公开
标题翻译：含有碳或氮的二极体的非挥发性记忆体装置及其制备方法
公开(公告)号：WO2009002476A3
公开(公告)日：2009-03-05
申请号：PCT/US2008007801
申请日：2008-06-23
申请人： SANDISK 3D LLC , HERNER S BRAD , CLARK MARK H , KUMAR TANMAY
发明人： HERNER S BRAD , CLARK MARK H , KUMAR TANMAY
IPC分类号： H01L27/102 , G11C11/36 , H01L27/06 , H01L29/04 , H01L29/161 , H01L29/167 , H01L29/26 , H01L29/861 , H01L29/868
CPC分类号： H01L29/868 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C17/165 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021 , H01L29/04 , H01L29/161 , H01L29/167 , H01L29/66136 , H01L29/8615
摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode (2) which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration. The carbon and/or nitrogen is introduced for example into the intrinsic region (6) of a p-i-n diode (4,6,8).
摘要翻译：非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管（2），其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。将碳和/或氮引入例如p-i-n二极管（4,6,8）的本征区域（6）中。

10. 发明申请

WO2008016833A3 INCREASING WRITE VOLTAGE PULSE OPERATIONS IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中增加写入电压脉冲运算
公开(公告)号：WO2008016833A3
公开(公告)日：2008-07-17
申请号：PCT/US2007074507
申请日：2007-07-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , KUMAR TANMAY
发明人： SCHEUERLEIN ROY E , KUMAR TANMAY
IPC分类号： G11C13/00 , G11C11/56 , G11C17/16
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72
摘要： A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.
摘要翻译：提供了一种无源元件存储器件，其包括由与转向元件串联的状态改变元件构成的存储单元。受控脉冲操作用于执行与存储器单元阵列中的置位和复位操作相关的电阻变化。在一个实施例中，通过对所选择的第一阵列线施加正电压脉冲同时向所选择的第二阵列线施加负电压脉冲，将阵列中的选定存储单元切换到目标电阻状态。可以增加电压脉冲的幅度，同时施加以有效和安全地切换具有不同操作特性的电池的电阻。在实施例中，电池经受反向偏置以降低泄漏电流并增加带宽。在一些实施例中，电压脉冲的幅度和持续时间与在选择的存储器单元上施加的电流一起被控制。这些受控的基于脉冲的操作可以用于在各种实施例中将存储器单元设置为较低的电阻状态或将存储器单元重置为更高的电阻状态。

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