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1. 发明申请

WO2011056534A3 METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING 审中-公开
公开(公告)号：WO2011056534A3
公开(公告)日：2011-05-12
申请号：PCT/US2010/054027
申请日：2010-10-26
申请人： SANDISK 3D, LLC , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J. , TANAKA, Yoichiro
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J. , TANAKA, Yoichiro
IPC分类号： H01L21/033 , H01L27/10 , H01L27/02 , H01L27/06
摘要： The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

2. 发明申请

WO2011056527A2 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 审中-公开
标题翻译：用于降低成本图案的三维矩阵阵列存储器布局方法和装置
公开(公告)号：WO2011056527A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/054013
申请日：2010-10-26
申请人： SANDISK 3D, LLC , SCHEUERLEIN, Roy E. , PETTI, Christopher J. , TANAKA, Yoichiro
发明人： SCHEUERLEIN, Roy E. , PETTI, Christopher J. , TANAKA, Yoichiro
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了用于三维存储器的存储层布局的装置，方法和系统。存储器层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储器线; 以及用于将存储器层耦合到三维存储器中的其他存储器层的多个齐触点区域。存储器线从存储器阵列块延伸并且使用侧壁限定的过程形成。存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。齐亚接触区的尺寸大约是存储器线的半间距尺寸的四倍。存储器线被布置成适合于允许单个存储器线与单个zia接触区相交并且为其他zia接触区提供其他存储器线之间的区域的图案。披露了许多其他方面。

3. 发明申请

WO2011056529A2 APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING 审中-公开
标题翻译：使用双重格式化方式形成记忆线和结构的四种方法的设备和方法
公开(公告)号：WO2011056529A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/054017
申请日：2010-10-26
申请人： SANDISK 3D, LLC , SCHEUERLEIN, Roy, E. , TANAKA, Yoichiro
发明人： SCHEUERLEIN, Roy, E. , TANAKA, Yoichiro
IPC分类号： H01L21/033
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译：本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。公开了许多附加方面。

4. 发明申请

WO2008121674A1 DIFFUSION BARRIER IN 3D MEMORY AND METHOD FOR IMPLEMENTING 审中-公开
标题翻译：三维存储器中的扩散障碍和实现方法
公开(公告)号：WO2008121674A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/058358
申请日：2008-03-27
申请人： SANDISK 3D LLC , TANAKA, Yoichiro
发明人： TANAKA, Yoichiro
IPC分类号： H01L21/8247 , H01L21/3205
CPC分类号： H01L27/1021 , H01L21/76846 , H01L21/76849 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
摘要翻译：在三维或三维存储单元中的一个或多个导体周围形成一个或多个扩散屏障。扩散阻挡层允许导体包括非常低电阻率的材料，例如铜，其可能会散布到周围区域，特别是在升高的处理温度下。利用较低电阻率的材料允许通过减少当导体尺寸减小时发生的电阻增加来减小器件尺寸。因此，可以在给定区域上产生更多的单元，从而增加所得到的存储器阵列的密度和存储容量。

5. 发明申请

WO2010059672A1 INTEGRATION OF DAMASCENE TYPE DIODES AND CONDUCTIVE WIRES FOR MEMORY DEVICE 审中-公开
标题翻译：大容量二极管和存储器件导电线的集成
公开(公告)号：WO2010059672A1
公开(公告)日：2010-05-27
申请号：PCT/US2009/064915
申请日：2009-11-18
申请人： SANDISK 3D LLC , TANAKA, Yoichiro
发明人： TANAKA, Yoichiro
IPC分类号： H01L27/102
CPC分类号： H01L27/1021
摘要： A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.
摘要翻译：制造半导体器件的方法包括在衬底上形成第一导电型多晶硅层，在第一导电型多晶硅层上形成绝缘层，其中绝缘层包括暴露第一导电型多晶硅层的开口，并形成内在的在第一导电型多晶硅层的开口中的多晶硅层。非易失性存储器件包括第一电极，位于与第一电极电接触的操作元件，具有位于操舵元件上方的U形横截面形状的存储元件和位于与存储元件电接触的第二电极。

6. 发明申请

WO2011008767A2 METHOD OF MAKING DAMASCENE DIODES USING SACRIFICIAL MATERIAL 审中-公开
标题翻译：使用牺牲材料制造大马士革二极管的方法
公开(公告)号：WO2011008767A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/041836
申请日：2010-07-13
申请人： SANDISK 3D LLC , MAKALA, Raghuveer , DUNTON, Vance , TANAKA, Yoichiro , MAXWELL, Steven , ZHANG, Tong , RADIGAN, Steven, J.
发明人： MAKALA, Raghuveer , DUNTON, Vance , TANAKA, Yoichiro , MAXWELL, Steven , ZHANG, Tong , RADIGAN, Steven, J.
IPC分类号： H01L27/10
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
摘要翻译：制造半导体器件的方法包括：在底层上形成包括种子材料的第一层;在第一层上形成包括牺牲材料的第二层，牺牲材料不同于种子将第一层和第二层图案化成多个分离的特征;在多个分离的特征之间形成绝缘填充材料;从分离的特征移除牺牲材料以在绝缘填充材料中形成多个开口; 种子材料暴露在多个开口中，并且在暴露的种子材料上在多个开口中生长半导体材料。

7. 发明申请

WO2009088890A2 MEMORY CELL WITH PLANARIZED CARBON NANOTUBE LAYER AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有平面化碳纳米管层的存储器单元及其形成方法
公开(公告)号：WO2009088890A2
公开(公告)日：2009-07-16
申请号：PCT/US2008/088586
申请日：2008-12-30
申请人： SANDISK 3D, LLC , SCHRICKER, April , CLARK, Mark , HERNER, Brad , TANAKA, Yoichiro
发明人： SCHRICKER, April , CLARK, Mark , HERNER, Brad , TANAKA, Yoichiro
IPC分类号： H01L21/8247 , H01L27/11
CPC分类号： H01L51/0595 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G11C13/0014 , G11C13/025 , G11C2213/71 , G11C2213/72 , H01L21/31053 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L51/0048 , H01L51/0587 , H01L51/0591
摘要： In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) fabricating a carbon nano- tube (CNT) material above the first conductor; (3) depositing a dielectric material onto a top surface of the CNT material; (4) planarizing the dielectric material to expose at least a portion of the CNT material; (5) fabricating a diode above the first conductor; and (6) fabricating a second conductor above the CNT material and the diode. Numerous other aspects are provided.
摘要翻译：在一些方面中，提供一种制造存储器单元的方法，其包括（1）在衬底上制造第一导体; （2）在第一导体上方制造碳纳米管（CNT）材料; （3）将电介质材料沉积到CNT材料的顶表面上; （4）平面化电介质材料以暴露至少一部分CNT材料; （5）在第一导体上方制造二极管; 和（6）在CNT材料和二极管上制造第二导体。还提供了许多其他方面。

8. 发明申请

WO2009045348A1 LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY 审中-公开
标题翻译：内存中的TUNGSTEN /二氧化硅界面
公开(公告)号：WO2009045348A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/011216
申请日：2008-09-26
申请人： SANDISK 3D LLC , TANAKA, Yoichiro , RADIGAN, Steven, J. , RAGHURAM, Usha
发明人： TANAKA, Yoichiro , RADIGAN, Steven, J. , RAGHURAM, Usha
IPC分类号： H01L27/102
CPC分类号： H01L27/101 , H01L27/1021
摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
摘要翻译：半导体晶片组件包括电介质基体。一层硅沉积在其上。金属硬掩模沉积在硅上。电介质硬掩模沉积在金属硬掩模上。光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

9. 发明授权

EP2191508B1 LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY 失效转让
标题翻译： COVER用于在存储器中钨/二氧化硅接口
公开(公告)号：EP2191508B1
公开(公告)日：2011-06-29
申请号：EP08836145.6
申请日：2008-09-26
申请人： Sandisk 3D LLC
发明人： TANAKA, Yoichiro , RADIGAN, Steven, J. , RAGHURAM, Usha
IPC分类号： H01L21/8229 , H01L27/102
CPC分类号： H01L27/101 , H01L27/1021
摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.

10. 发明公开

EP2494586A2 APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING 审中-公开
标题翻译： DEVICE AND METHOD FOR MEMORY线及生产和双侧板构造4X半间距浮雕结构构造
公开(公告)号：EP2494586A2
公开(公告)日：2012-09-05
申请号：EP10774374.2
申请日：2010-10-26
申请人： Sandisk 3D LLC
发明人： SCHEUERLEIN, Roy, E. , TANAKA, Yoichiro
IPC分类号： H01L21/033
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

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