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1. 发明授权

US08993439B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08993439B2
公开(公告)日：2015-03-31
申请号：US14285969
申请日：2014-05-23
申请人： Samsung Electronics Co., Ltd.
发明人： Yong-Jun Kim , Kil-Ho Lee , Ki-Joon Kim , Myoung-Su Son
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76807
摘要： A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.
摘要翻译：一种制造半导体器件的方法，包括形成模制层; 在成型层上形成镶嵌掩模层和掩模层; 通过蚀刻掩模层形成掩模层图案; 通过部分蚀刻镶嵌掩模层形成镶嵌图案; 在掩模层图案上形成镶嵌掩模层以埋藏镶嵌图案; 通过蚀刻镶嵌掩模层和掩模层图案形成部分地与镶嵌图案重叠的镶嵌图案; 通过去除由镶嵌图案暴露的掩模层图案的一部分来连接镶嵌图案和镶嵌图案; 在镶嵌掩模层上形成镶嵌掩模层，以埋藏镶嵌图案; 以及通过使用掩模层图案的剩余部分蚀刻镶嵌掩模层和模制层，在镶嵌图案之下形成沟槽。

2. 发明授权

US11158671B2 Semiconductor devices 有权
公开(公告)号：US11158671B2
公开(公告)日：2021-10-26
申请号：US16435915
申请日：2019-06-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yong-Jae Kim , Kil-Ho Lee , Dae-Eun Jeong , Gwan-Hyeob Koh
IPC分类号： H01L43/02 , H01L43/12 , H01L27/22 , H01L21/768
摘要： A semiconductor device may include a conductive structure on a substrate, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. A lower surface of the contact plug may have an area greater than that of an upper surface thereof, and the contact plug may include a capping pattern at least partially covering an upper surface of the conductive structure, a conductive pattern on the capping pattern, and an amorphous metal pattern on the conductive pattern.

3. 发明授权

US09754817B2 Semiconductor structures having an insulative island structure 有权
公开(公告)号：US09754817B2
公开(公告)日：2017-09-05
申请号：US15170043
申请日：2016-06-01
申请人： Samsung Electronics Co., Ltd.
发明人： Kil-Ho Lee , Se-Woong Park , Ki-Joon Kim
IPC分类号： H01L21/02 , H01L21/30 , H01L29/06 , H01L33/00 , H01L27/10 , H01L21/768 , H01L23/528 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7681 , H01L21/76804 , H01L21/76808 , H01L21/76816 , H01L21/76843 , H01L21/76879 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

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