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1. 发明申请

US20190189744A1 SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20190189744A1
公开(公告)日：2019-06-20
申请号：US16274350
申请日：2019-02-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L27/12 , H01L27/088 , H01L21/768 , H01L23/528 , H01L23/522
CPC分类号： H01L29/0847 , H01L21/7682 , H01L21/76834 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76885 , H01L23/5222 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L27/0886 , H01L27/1211
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

2. 发明授权

US10217820B2 Semiconductor devices 有权
公开(公告)号：US10217820B2
公开(公告)日：2019-02-26
申请号：US15632884
申请日：2017-06-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/088 , H01L27/12
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

3. 发明申请

US20170358519A1 Semiconductor Device and Method of Fabricating the Same 审中-公开
公开(公告)号：US20170358519A1
公开(公告)日：2017-12-14
申请号：US15669280
申请日：2017-08-04
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-Nam Kim , Tsukasa Matsuda , Rak-Hwan Kim , Byung-Hee Kim , Nae-In Lee , Jong-Jin Lee
IPC分类号： H01L23/485 , H01L23/498 , H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L23/485 , H01L21/7684 , H01L21/76846 , H01L21/76849 , H01L21/76882 , H01L23/49822 , H01L23/49866 , H01L23/5226 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.

4. 发明授权

US09812450B2 Semiconductor devices and methods of manufacturing the same 有权
公开(公告)号：US09812450B2
公开(公告)日：2017-11-07
申请号：US15006265
申请日：2016-01-26
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Min Baek , Sang-Hoon Ahn , Woo-Kyung You , Byung-Hee Kim , Young-Ju Park , Nae-in Lee , Kyung-Min Chung
IPC分类号： H01L23/522 , H01L27/088 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823475
摘要： A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

5. 发明申请

US20170133317A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20170133317A1
公开(公告)日：2017-05-11
申请号：US15298855
申请日：2016-10-20
申请人： Samsung Electronics Co., Ltd.
发明人： Rak-Hwan KIM , Byung-Hee Kim , Jin-Nam Kim , Jong-Min Baek , Nae-In Lee , Eun-Ji Jung
IPC分类号： H01L23/528 , H01L23/532 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5283 , H01L21/76847 , H01L21/76877 , H01L23/53209 , H01L23/53238 , H01L23/53261 , H01L23/53266
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.

6. 发明授权

US10199263B2 Semiconductor devices and methods of manufacturing the same 有权
公开(公告)号：US10199263B2
公开(公告)日：2019-02-05
申请号：US15616334
申请日：2017-06-07
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sang-Shin Jang , Woo-Kyung You , Kyu-Hee Han , Jong-Min Baek , Viet Ha Nguyen , Byung-Hee Kim
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
摘要： A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

7. 发明授权

US10008407B2 Methods of manufacturing semiconductor devices including conductive structures 有权
公开(公告)号：US10008407B2
公开(公告)日：2018-06-26
申请号：US14955988
申请日：2015-12-01
申请人： Samsung Electronics Co., Ltd
发明人： Woo-Jin Lee , Byung-Hee Kim , Sang-Hoon Ahn , Woo-Kyung You , Jong-Min Baek , Nae-In Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76807 , H01L21/76816 , H01L21/76849 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2221/1047
摘要： A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

8. 发明授权

US09728604B2 Semiconductor devices 有权
公开(公告)号：US09728604B2
公开(公告)日：2017-08-08
申请号：US15059438
申请日：2016-03-03
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/088 , H01L27/12
CPC分类号： H01L29/0847 , H01L21/7682 , H01L21/76834 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76885 , H01L23/5222 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L27/0886 , H01L27/1211
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

9. 发明申请

US20140264892A1 SEMICONDUCTOR DEVICE WITH DUMMY LINES 有权
标题翻译：半导体器件与DUMMY线
公开(公告)号：US20140264892A1
公开(公告)日：2014-09-18
申请号：US13840694
申请日：2013-03-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Tae-Soo Kim , Byung-Hee Kim
IPC分类号： H01L23/00
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/528 , H01L23/585 , H01L27/0207 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction. A plurality of first sub straps is branched from the first main strap. The plurality of second sub straps is branched from the second main strap. The plurality of dummy lines is positioned between the first main strap and the second main strap. Each of the plurality of dummy lines is positioned between each of the plurality of first sub straps and each of the plurality of second sub straps. Each of the dummy lines is spaced apart from the first main strap, the second main strap, each of the first sub straps and each of the second sub straps.
摘要翻译：半导体器件包括第一主带，第二主带，多个第一子带，多个第二子带和多个虚线。第一主带在第一方向延伸。第二主带在第一个方向延伸。多个第一子带从第一主带分支。多个第二子带从第二主带分支。多个假线位于第一主带和第二主带之间。多个虚拟线中的每一个位于多个第一子带中的每一个与多个第二子带中的每一个之间。每条虚线与第一主带，第二主带，每个第一子带和每个第二子带间隔开。

10. 发明授权

US10777449B2 Methods of manufacturing semiconductor devices 有权
公开(公告)号：US10777449B2
公开(公告)日：2020-09-15
申请号：US16242483
申请日：2019-01-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sang-Shin Jang , Woo-Kyung You , Kyu-Hee Han , Jong-Min Baek , Viet Ha Nguyen , Byung-Hee Kim
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528
摘要： A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

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