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1. 发明专利

FR2982697A3 Curved display device e.g. LCD device, has a display screen having different curvatures with different radius of curvature that corresponds to radius of a circular arc which intersects with the corresponding segment of display screen 未知
公开(公告)号：FR2982697A3
公开(公告)日：2013-05-17
申请号：FR1351150
申请日：2013-02-11
申请人： SAMSUNG ELECTRONICS CO LTD , SAMSUNG DISPLAY CO LTD
发明人： AN JUN-SEOK , KIM DONG-WOOK , KIM SUNG-HWAN , PARK JEE-SU , PARK CHAN-HONG , SIM BYUNG-KOOK , LEE JONG-CHEOL , LEE CHEOL-SE , CHOI HYEONG-SIK , AHN BYUNG WOOK , LEE CHEONG HUN
IPC分类号： G09G3/36 , G09F9/37
摘要： The display device (100) comprises a display screen (DP1) for displaying images. The display screen has different curvatures at different segments (HR1-HR3). Each of the different curvatures has different radius of curvature that corresponds to a radius of a circular arc which intersects with the corresponding segment. The display screen is fixed using a fixing element (FM1), such that the display screen has different curvatures. The curvature at the center of the screen is greater than the curvature at the edge portion of screen.

2. 发明专利

JP2013242525A Curved surface display device 审中-公开
标题翻译：弯曲表面显示装置
公开(公告)号：JP2013242525A
公开(公告)日：2013-12-05
申请号：JP2013048924
申请日：2013-03-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd. , Samsung Display Co Ltd , サムスンディスプレイカンパニーリミテッド
发明人： AN JUN SEOK , KIM DONG WOOK , KIM SUNG-HWAN , PARK JI-SOO , PARK CHAN-HONG , SIM BYUNG-KOOK , LEE JONG-CHEOL , LEE CHEOL-SE , CHOI HYUNG-SIK , AHN BYUNG-WOOK , LEE JUNG-HOON
IPC分类号： G02F1/1333 , F21S2/00 , F21Y101/02 , F21Y103/00
CPC分类号： G02F1/133308 , F21V33/0052 , G02F1/133305 , G02F1/13336 , G02F1/133602 , G02F1/136286 , G02F2001/13332 , G02F2001/133328 , H05K5/0017 , H05K5/02 , H05K5/0217
摘要： PROBLEM TO BE SOLVED: To provide a curved surface display device for preventing an unevenness defect and a yellowish defect to be generated by stress of a bent display panel.SOLUTION: A curved surface display device 100 includes a display screen for displaying a video, in which the display screen has different curvatures in a plurality of sections, the curvatures have different curvature radii HR1, HR2, HR3, and each of the curvature radii corresponds to a radius of a circular arc approximated to a curve crossing a corresponding section.
摘要翻译：要解决的问题：提供一种用于防止由弯曲的显示面板的应力产生的不均匀性缺陷和黄色缺陷的曲面显示装置。解决方案：曲面显示装置100包括用于显示视频的显示屏，显示屏幕在多个部分中具有不同的曲率，曲率具有不同的曲率半径HR1，HR2，HR3，并且每个曲率半径对应于近似于与相应部分交叉的曲线的圆弧的半径。

3. 发明专利

FR2982697B3 未知
公开(公告)号：FR2982697B3
公开(公告)日：2014-03-14
申请号：FR1351150
申请日：2013-02-11
申请人： SAMSUNG ELECTRONICS CO LTD , SAMSUNG DISPLAY CO LTD
发明人： AN JUN-SEOK , KIM DONG-WOOK , KIM SUNG-HWAN , PARK JEE-SU , PARK CHAN-HONG , SIM BYUNG-KOOK , LEE JONG-CHEOL , LEE CHEOL-SE , CHOI HYEONG-SIK , AHN BYUNG WOOK , LEE CHEONG HUN
IPC分类号： G09G3/36 , G09F9/37

4. 发明专利

JP2007041518A Liquid crystal display device and controlling method thereof 审中-公开
标题翻译：液晶显示装置及其控制方法
公开(公告)号：JP2007041518A
公开(公告)日：2007-02-15
申请号：JP2006086626
申请日：2006-03-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JANG HYEON-YONG , LEE JONG-CHEOL
IPC分类号： G02F1/133
CPC分类号： H05B33/0854 , H05B33/0851 , H05B33/089 , H05B33/0896 , H05B41/282 , H05B41/285
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of controlling a supply time of high current to a surface light source, and to provide a controlling method of the liquid crystal display device. SOLUTION: The liquid crystal display device comprises: a backlight; an inverter which drives the backlight and supplies a high current to the backlight; and an inverter controller which shuts down the inverter when the supply time of the high current from the inverter to the backlight exceeds an allowable time and changes the allowable time in accordance with an ambient temperature while the the high current is supplied from the inverter to the backlight. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种能够控制向面光源的高电流供给时间的液晶显示装置，提供液晶显示装置的控制方法。液晶显示装置包括：背光源; 驱动背光并向背光供给高电流的逆变器; 以及逆变器控制器，当从逆变器到背光源的高电流的供给时间超过允许时间时，在从逆变器供给高电流的同时，根据环境温度改变允许时间，从而关闭逆变器背光源。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2008159248A Sense amplifier circuit of semiconductor memory device and method of operating the same 审中-公开
标题翻译：半导体存储器件的感测放大器电路及其操作方法
公开(公告)号：JP2008159248A
公开(公告)日：2008-07-10
申请号：JP2007330481
申请日：2007-12-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM MYEONG-O , KIM SOO-HWAN , LEE JONG-CHEOL
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide a sense amplifier circuit of a semiconductor memory device and a method of operating the same. SOLUTION: The sense amplifier circuit includes a bit line sense amplifier connected with a big line to sense and amplify a signal of the bit line, and a calibration circuit for calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier includes a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供半导体存储器件的读出放大器电路及其操作方法。解决方案：读出放大器电路包括与大线连接的位线读出放大器，用于感测和放大位线的信号;以及校准电路，用于基于逻辑门限值校准位线的电压电平的位线读出放大器。位线检测放大器在校准位线的电压电平后，感测并放大位线的信号。位线读出放大器包括2级级联锁存器，其包括具有与位线连接的输入端的第一反相器; 以及第二反相器，其具有与第一反相器的输出端子连接的输入端子和与位线连接的输出端子，并且响应于感测控制信号而被允许/禁止。校准电路包括开关元件，其连接在第一反相器的输出端和位线之间，并响应于校准控制信号而导通或截止。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2005209333A Method and circuit for sampling data in semiconductor memory device 有权
标题翻译：用于在半导体存储器件中采样数据的方法和电路
公开(公告)号：JP2005209333A
公开(公告)日：2005-08-04
申请号：JP2005000860
申请日：2005-01-05
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： IN YOSHIN , LEE JONG-CHEOL , CHO UK-RAE
IPC分类号： G11C11/417 , G11C7/10 , G11C11/40 , H04L7/00
CPC分类号： G11C7/1087 , G11C7/1072 , G11C7/1078 , G11C7/1093
摘要： PROBLEM TO BE SOLVED: To provide a method and circuit for sampling data in a DDR (double data rate) system memory. SOLUTION: The method for sampling data in a DDR mode semiconductor memory includes a step for successively inputting first to fourth data in synchronization with a first rising or falling edge of an external clock signal in write instruction, a step for sampling the first and the second data on the first and the second paths, respectively, in response to a first path controlling signal generated in synchronization with a second falling edge of the external clock signal, a step for writing the first and the second data in a memory cell in response to write clock generated in synchronization with a third rising edge of the external clock signal, a step for sampling the third and the fourth data on the second and the first paths, respectively, in response to a second path controlling signal generated in synchronization with a third falling edge of the external clock signal and a step for writing the fourth data of the first path and the third data of the second path in the memory cell in response to a write clock generated in synchronization with a fourth rising edge of the external clock signal. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于在DDR（双倍数据速率）系统存储器中采样数据的方法和电路。解决方案：用于在DDR模式半导体存储器中采样数据的方法包括与写入指令中的外部时钟信号的第一上升沿或下降沿同步地连续输入第一至第四数据的步骤，用于对第一以及响应于与外部时钟信号的第二下降沿同步产生的第一路径控制信号，分别在第一和第二路径上的第二数据，将第一和第二数据写入存储单元的步骤响应于与外部时钟信号的第三上升沿同步而产生的写时钟，响应于同步产生的第二路径控制信号，分别对第二和第一路径上的第三和第四数据进行采样的步骤具有外部时钟信号的第三下降沿，并且将第一路径的第四数据和第二路径的第三数据写入存储单元的步骤响应于与外部时钟信号的第四上升沿同步产生的写入时钟。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

DE102012103623A8 Verfahren zum Bilden einer Oxidschicht und Verfahren zum Herstellen einer Halbleitervorrichtung mit der Oxidschicht 未知
公开(公告)号：DE102012103623A8
公开(公告)日：2013-07-18
申请号：DE102012103623
申请日：2012-04-25
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG SUK-JIN , KIM YOUN-SOO , KANG SANG-YEOL , YOO CHA-YOUNG , LEE JONG-CHEOL
IPC分类号： H01L21/316 , H01L21/8242

8. 发明专利

DE10148904A1 未知
公开(公告)号：DE10148904A1
公开(公告)日：2002-08-29
申请号：DE10148904
申请日：2001-09-25
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE KWANG-JIN , LEE JONG-CHEOL
IPC分类号： G11C29/00 , G11C7/06 , G11C7/08 , G11C7/10 , G11C29/02
摘要： An apparatus for controlling an enable of a sense amplifier in a semiconductor memory device includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.

9. 发明专利

SG104289A1 MEMORY ARCHITECTURE PERMITTING SELECTION OF STORAGE DENSITY AFTER FABRICATION OF ACTIVE CIRCUITRY 未知
公开(公告)号：SG104289A1
公开(公告)日：2004-06-21
申请号：SG200107525
申请日：2001-12-05
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM SU-CHUL , BYUN HYUN-GEUN , LEE KWANG-JIN , LEE JONG-CHEOL , CHO UKRAE
IPC分类号： H01L21/301 , H01L21/82 , H01L27/02 , H01L27/10 , H01L27/108 , G06F17/50
摘要： A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced by connecting different numbers of memory units on the generic wafer by forming one or more interconnect layers specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different mask sets that form a different conductive pattern for each storage capacity or by forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips.

10. 发明专利

DE10148904B4 未知
公开(公告)号：DE10148904B4
公开(公告)日：2006-05-18
申请号：DE10148904
申请日：2001-09-25
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE KWANG-JIN , LEE JONG-CHEOL
IPC分类号： G11C7/08 , G11C29/00 , G01R31/3187 , G11C7/06 , G11C7/10 , G11C29/02
摘要： An apparatus for controlling an enable of a sense amplifier in a semiconductor memory device includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.

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