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    • 4. 发明申请
    • APPARATUS AND METHOD FOR VARIABLE FAST FOURIER TRANSFORM
    • 用于可变快速傅立叶变换的装置和方法
    • WO2008069382A2
    • 2008-06-12
    • PCT/KR2007002950
    • 2007-06-18
    • KOREA ELECTRONICS TELECOMMSAMSUNG ELECTRONICS CO LTDMOON YOUNG-JINKIM HYUN-JAEKIM KI-SEOKKIM YOUNG-IL
    • MOON YOUNG-JINKIM HYUN-JAEKIM KI-SEOKKIM YOUNG-IL
    • G06F17/14
    • G06F17/142
    • The present invention relates to an apparatus and method for variable fast Fourier transform. According to an embodiment of the present invention, two n-point fast Fourier transform (FFT) processors are used to generate two n-point FFT output data or one 2n-point FFT output data. The one 2n-point input data is alternately input to the two n-point FFT processors. Each of the two n-point FFT processors selects a twiddle factor for the n-point input data or the 2n-point input data and performs fast Fourier transform. A butterfly operation is performed on signals obtained by performing fast Fourier transform on the 2n-point input data signal, and the processed signals are aligned in an output order. According to this structure, it is possible to realize a fast Fourier transform hardware engine that selectively performs multi-frequency allocation in a base station system that supports the multi-frequency allocation.
    • 本发明涉及一种用于可变快速傅里叶变换的装置和方法。 根据本发明的实施例,使用两个n点快速傅里叶变换(FFT)处理器来产生两个n点FFT输出数据或一个2n点FFT输出数据。 一个2n点输入数据交替地输入到两个n点FFT处理器。 两个n点FFT处理器中的每一个为n点输入数据或2n点输入数据选择旋转因子,并执行快速傅里叶变换。 对通过对2n点输入数据信号执行快速傅里叶变换获得的信号执行蝶形运算,并且处理的信号以输出顺序对准。 根据该结构,能够实现在支持多频分配的基站系统中选择性地进行多频分配的快速傅里叶变换硬件引擎。
    • 5. 发明申请
    • MIXCOLUMN BLOCK DEVICE AND METHOD OF PERFORMING MULTIPLICATION CALCULATION USING THE SAME
    • MIXCOLUMN块装置及使用其进行多项式计算的方法
    • WO2008069386A3
    • 2009-07-30
    • PCT/KR2007003027
    • 2007-06-21
    • KOREA ELECTRONICS TELECOMMSAMSUNG ELECTRONICS CO LTDOH JUNG-HOONKIM HYUN-JAEKIM YOUNG-IL
    • OH JUNG-HOONKIM HYUN-JAEKIM YOUNG-IL
    • H04L9/06
    • H04L9/0631H04L2209/12
    • The present invention relates to a MixColumn block device and a method of performing a multiplication operation using the same. According to an exemplary embodiment of the present invention, a MixColumn block device includes a storage unit that stores input data of a bit unit as a byte unit and outputs stored input bytes, a first multiplication operation block unit that performs and outputs multiplication operations of {01 } and {02} as hexadecimal values for the input bytes that are received from the storage unit, a second multiplication operation block unit that performs and outputs multiplication operations of {01 }, {02}, and {03} as hexadecimal values by using the {01 } and {02} multiplication operation results received from the first multiplication operation block unit, and an exclusive logical sum operation unit that performs an exclusive logical sum operation on the {01 }, {02}, and {03} multiplication operation results received from the second multiplication operation block unit and outputs output bytes for the input bytes.
    • 本发明涉及一种MixColumn块装置和使用该装置进行乘法运算的方法。 根据本发明的示例性实施例,MixColumn块装置包括:存储单元,其将位单元的输入数据存储为字节单元并输出存储的输入字节;第一乘法运算块单元,其执行并输出{ 01}和{02}作为从存储单元接收的输入字节的十六进制值,第二乘法运算块单元,其执行并输出{01},{02}和{03}的乘法运算作为十六进制值,由 使用从第一乘法运算块单元接收的{01}和{02}乘法运算结果,以及对{01},{02}和{03}乘法执行异或运算的异或逻辑和运算单元 从第二乘法运算块单元接收到运算结果,输出输入字节的输出字节。
    • 7. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列
    • WO2004042781A3
    • 2004-09-30
    • PCT/KR0302346
    • 2003-11-04
    • SAMSUNG ELECTRONICS CO LTDLEE SU-GYEONGKANG SOOK-YOUNGKANG MYUNG-KOOKIM HYUN-JAEIM JAMES S
    • LEE SU-GYEONGKANG SOOK-YOUNGKANG MYUNG-KOOKIM HYUN-JAEIM JAMES S
    • G02F1/136H01L21/77H01L27/12H01L29/786
    • H01L27/1285H01L27/1214H01L27/1296H01L29/78645
    • A thin film transistor array panel is provided, which includes: a substrate (110) including a plurality of pixel areas; a semiconductor layer (140, 142) formed on the substrate (110) and including a plurality of pairs of first (140) and second (142) semiconductor portions in respective pixel areas; a first insulating layer (130) formed on the semiconductor layer; a gate wire (121-124); formed on the first insulating layer; a second insulating layer (180) formed on the gate wire (121-124); a data wire (171, 172) formed on the second insulating layer (180); a third insulating layer (185) formed on the data wire (171, 172) a pixel electrode (192) formed on the third insulating layer (185) and connected to the data wire (171, 172), wherein width and length of at least one of the first (140) and the second (142) semiconductor portions vary between at least two pixel areas.
    • 提供薄膜晶体管阵列面板,其包括:包括多个像素区域的基板(110); 形成在所述基板(110)上并在各像素区域中包括多对第一(140)和第二(142)半导体部分的半导体层(140,142) 形成在所述半导体层上的第一绝缘层(130) 栅极线(121-124); 形成在第一绝缘层上; 形成在栅极导线(121-124)上的第二绝缘层(180); 形成在第二绝缘层(180)上的数据线(171,172); 形成在数据线(171,172)上的形成在第三绝缘层(185)上并连接到数据线(171,172)的像素电极(192)的第三绝缘层(185),其中宽度和长度为 第一(140)和第二(142)半导体部分中的至少一个在至少两个像素区域之间变化。