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1. 发明申请

WO2010002516A3 LOW-COST DOUBLE STRUCTURE SUBSTRATES AND METHODS FOR THEIR MANUFACTURE 审中-公开
公开(公告)号：WO2010002516A3
公开(公告)日：2010-01-07
申请号：PCT/US2009/044825
申请日：2009-05-21
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , NGUYEN, Bich-yen , MAZURE, Carlos
发明人： NGUYEN, Bich-yen , MAZURE, Carlos
IPC分类号： H01L21/20
摘要： In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

2. 发明申请

WO2010002515A2 LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE 审中-公开
标题翻译：具有高电阻特性的低成本基板及其制造方法
公开(公告)号：WO2010002515A2
公开(公告)日：2010-01-07
申请号：PCT/US2009/044810
申请日：2009-05-21
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , MAZURE, Carlos , NGUYEN, Bich-yen
发明人： MAZURE, Carlos , NGUYEN, Bich-yen
IPC分类号： H01L21/20
CPC分类号： H01L21/76251
摘要： In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.
摘要翻译：在一个实施例中，本发明提供了被构造成使得在其顶层中制造的器件具有与在标准高电阻率衬底中制造的相同器件相似的性质的衬底。本发明的基板包括具有标准电阻率的支撑体，布置在支撑基板上的具有高电阻率，优选地大于约1000欧姆 - 厘米的半导体层，布置在高电阻率层上的绝缘层，以及顶层布置在绝缘层上。本发明还提供了制造这种基底的方法。

3. 发明申请

WO2007130728A2 ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR ISLANDS OF DIFFERENT THICKNESSES OVER AN INSULATING LAYER AND A PROCESS OF FORMING THE SAME 审中-公开
标题翻译：包含绝缘层的半导体岛的电子器件及其形成方法
公开(公告)号：WO2007130728A2
公开(公告)日：2007-11-15
申请号：PCT/US2007/062534
申请日：2007-02-22
申请人： FREESCALE SEMICONDUCTOR INC. , SADAKA, Mariam, G. , NGUYEN, Bich-yen , THEAN, Voon-yew
发明人： SADAKA, Mariam, G. , NGUYEN, Bich-yen , THEAN, Voon-yew
IPC分类号： H01L21/31
CPC分类号： H01L21/32 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/84
摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer (124) over a semiconductor layer (106) that overlies a substrate (100), and patterning the semiconductor layer to form a semiconductor island (202, 204, 206, 208). The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material (424) along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
摘要翻译：形成电子器件的工艺可以包括在覆盖在衬底（100）上的半导体层（106）上形成图案化的抗氧化层（124），并且图案化半导体层以形成半导体岛（202,204,206 ，208）。半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。该方法还可以包括沿着半导体岛的一侧形成抗氧化材料（424）或沿着半导体岛的一侧选择性地沉积半导体材料。该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛，并将抗氧化材料转化为含氧环境。

4. 发明申请

WO2007133870A2 SELECTIVE UNIAXIAL STRESS RELAXATION BY LAYOUT OPTIMIZATION IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT 审中-公开
标题翻译：绝缘子集成电路中应变硅中布线优化的选择性单相应力放松
公开(公告)号：WO2007133870A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/066436
申请日：2007-04-11
申请人： FREESCALE SEMICONDUCTOR INC. , NGUYEN, Bich-yen , THEAN, Voon-yew
发明人： NGUYEN, Bich-yen , THEAN, Voon-yew
IPC分类号： A47D5/00 , A47D9/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/0207 , H01L29/1033 , H01L29/41758 , H01L29/41775 , H01L29/6659 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： An integrated circuit (200) includes NMOS and PMOS transistors (220, 230). The NMOS (220) has a strained channel having first and second stress values along first and second axes respectively. The PMOS (230) has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS (220) and PMOS (230) have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS (220) may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS (230) may be less than the SA of the NMOS (220). The integrated circuit may include a tensile stressor of silicon nitride over the NMOS (220) and a compressive stressor of silicon nitride over the PMOS (230).
摘要翻译：集成电路（200）包括NMOS和PMOS晶体管（220,230）。 NMOS（220）具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS（230）具有沿第一和第二轴具有第三和第四应力值的应变通道。第一值应力与第三值不同，第二值与第四值不同。 NMOS（220）和PMOS（230）具有公共长度（L）和有效宽度（W），但扩散长度（SA）和/或源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS（220）可以包括位于栅极下方的有源层中的多个电介质结构。 PMOS（230）的SA可以小于NMOS（220）的SA。集成电路可以包括在NMOS（220）上的氮化硅的拉伸应力器和在PMOS（230）上的氮化硅的压应力。

5. 发明申请

WO2007092655A2 METHOD TO SELECTIVELY FORM REGIONS HAVING DIFFERING PROPERTIES AND STRUCTURE 审中-公开
标题翻译：选择具有不同性质和结构的区域的方法
公开(公告)号：WO2007092655A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/060259
申请日：2007-01-09
申请人： FREESCALE SEMICONDUCTOR INC. , SADAKA, Mariam, G. , NGUYEN, Bich-yen , THEAN, Voon-yew , WHITE, Ted, R.
发明人： SADAKA, Mariam, G. , NGUYEN, Bich-yen , THEAN, Voon-yew , WHITE, Ted, R.
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , Y10S438/973
摘要： A semiconductor device is formed having two physically separate regions (16, 28) with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer (16) having a first property is formed on an insulating layer (14). The first layer is isolated into first (16) and second (28) physically separate areas. After this physical separation, only the first area (28) is amorphized. A donor wafer (30) is placed in contact with the first (28) and second (16) areas. The semiconductor device (10) is annealed to modify the first (28) of the first (28) and second (16) separate areas to have a different property from the second of the first and second separate areas. The donor wafer (30) is removed and at least one semiconductor structure (32, 34) is formed in each of the first (28) and second (16) physically separate areas. In another form, the separate regions (114) are a bulk substrate (112) and an electrically isolated region (116) within the bulk substrate (112).
摘要翻译：半导体器件形成为具有两个具有不同性质的物理分离区域（16,28），例如不同的表面取向，晶体旋转，应变或组成。在一种形式中，在绝缘层（14）上形成具有第一特性的第一层（16）。第一层被分离成第一（16）和第二（28）物理上分开的区域。在这种物理分离之后，只有第一区域（28）是非晶化的。施主晶片（30）被放置成与第一（28）和第二（16）区域接触。半导体器件（10）被退火以修改第一（28）和第二（16）分离区域中的第一（28）与第一和第二分离区域中的第二个区域具有不同的性质。去除施主晶片（30），并且在第一（28）和第二（16）物理分离区域中的每一个中形成至少一个半导体结构（32,34）。在另一种形式中，独立区域（114）是本体衬底（112）内的体基板（112）和电隔离区域（116）。

6. 发明申请

WO2007092653A2 METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：WO2007092653A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/060145
申请日：2007-01-05
申请人： FREESCALE SEMICONDUCTOR INC. , ZHANG, Da , NGUYEN, Bich-yen
发明人： ZHANG, Da , NGUYEN, Bich-yen
CPC分类号： H01L21/823842 , H01L21/823814 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate (12) having a first doped region and a second doped region, providing a dielectric (14) over the first doped region and the second doped region, and forming a first gate stack (26) over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion (18) over the dielectric, a first in situ doped semiconductor portion (22) over the metal portion, and a first blocking cap (23) over the in situ doped semiconductor portion. The method further includes performing an implant to form source/drain regions adjacent the first gate stack, where the first blocking cap has a thickness sufficient to substantially block dopants from the implant from entering the first in situ doped semiconductor portion.
摘要翻译：一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底（12），在第一掺杂区域和第二掺杂区域上提供电介质（14），并形成第一栅叠层 26）在第一掺杂区域的至少一部分上方的电介质上。第一栅极堆叠包括电介质上的金属部分（18），金属部分上的第一原位掺杂半导体部分（22）和位于原位掺杂半导体部分上的第一阻挡盖（23）。该方法还包括执行植入物以形成邻近第一栅极叠层的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡来自植入物的掺杂剂进入第一原位掺杂半导体部分的厚度。

7. 发明申请

WO2006073624A1 SEMICONDUCTOR FABRICATION PROCESS INCLUDING RECESSED SOURCE/DRAIN REGIONS IN AN SOI WAFER 审中-公开
标题翻译：半导体制造工艺，包括SOI WAFER中的残留源/漏极区
公开(公告)号：WO2006073624A1
公开(公告)日：2006-07-13
申请号：PCT/US2005/043208
申请日：2005-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-yew , GOOLSBY, Brian, J. , NGUYEN, Bich-yen , NGUYEN, Thien T. , STEPHENS, Tab, A.
发明人： THEAN, Voon-yew , GOOLSBY, Brian, J. , NGUYEN, Bich-yen , NGUYEN, Thien T. , STEPHENS, Tab, A.
IPC分类号： H01R13/44 , H01R13/28 , H01R25/00
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer (101) includes forming isolation structures (110) in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer (104) of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric (120) is formed on the channel structure (143, 145) and a gate structure (140) is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures (160) are then grown epitaxially from exposed portions of the substrate bulk (102). The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片（101）中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构（110），其中隔离结构优选地延伸穿过有源层到晶片的BOX层（104）。去除有源层的上部以形成晶体管沟道结构。栅极电介质（120）形成在沟道结构（143,145）上，栅极结构（140）形成在栅极电介质上。执行栅极电介质，沟道结构和BOX层的暴露部分的蚀刻，然后从衬底体（102）的暴露部分外延生长源极/漏极结构（160）。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

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