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1. 发明申请

WO2011123199A1 BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME 审中-公开
标题翻译：粘结半导体结构及其形成方法
公开(公告)号：WO2011123199A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/025647
申请日：2011-02-22
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , MAZURE, Carlos , NGUYEN, Bich-Yen , SADAKA, Mariam
发明人： MAZURE, Carlos , NGUYEN, Bich-Yen , SADAKA, Mariam
IPC分类号： H01L27/06 , H01L21/822
CPC分类号： H01L27/0688 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/187 , H01L21/8221 , H01L2924/00011 , H01L2224/80001
摘要： Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
摘要翻译：形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且非晶膜可以被平坦化以形成一个或多个平坦化表面。半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

2. 发明申请

WO2010002509A1 SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：半导体结构
公开(公告)号：WO2010002509A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/044372
申请日：2009-05-18
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , NGUYEN, Bich-Yen , MAZURE, Carlos
发明人： NGUYEN, Bich-Yen , MAZURE, Carlos
IPC分类号： H01L27/12 , H01L21/70
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.
摘要翻译：在优选实施例中，本发明提供一种半导体结构，其具有半导电支撑件，布置在支撑件的一部分上的绝缘层和布置在绝缘层上的半导电表面层。电子器件可以形成在表面层中，也可以形成在衬底的半导体本体区域的未被绝缘层覆盖的露出部分中。本发明还提供了制造这样的半导体结构的方法，其从包括布置在连续绝缘层上的半导电表面层的衬底开始，两者均布置在半导电支撑件上，通过将至少一个选定区域基板，以形成基板的暴露的半导体本体区域。

3. 发明申请

WO2010002508A1 SUBSTRATE COMPRISING DIFFERENT TYPES OF SURFACES AND METHOD FOR OBTAINING SUCH SUBSTRATES 审中-公开
标题翻译：包含不同类型表面的基板和用于获得这种基板的方法
公开(公告)号：WO2010002508A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/044365
申请日：2009-05-18
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , NGUYEN, Bich-Yen
发明人： NGUYEN, Bich-Yen
IPC分类号： H01L27/04
CPC分类号： H01L21/76254 , H01L21/76256
摘要： A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.
摘要翻译：具有较大结晶缺陷密度的支撑体，设置在支撑体正面的第一区域上的绝缘层和设置在绝缘层上的表面层。可以至少在支撑体的前表面的第二区域上设置附加层，其厚度足以埋设支撑体的结晶缺陷。衬底还可以包括布置在支撑体的前表面的至少第一区域之间，在支撑体和绝缘层之间的外延层。此外，通过在表层的第一区域上形成掩模层并除去由掩模层未覆盖的第二区域中的表层和绝缘层来制造衬底的方法。附加层形成在第二区域中，然后平坦化。

4. 发明申请

WO2006107419A3 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2006107419A3
公开(公告)日：2006-10-12
申请号：PCT/US2006/005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
发明人： SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
IPC分类号： H01L21/8238
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

5. 发明申请

WO2006039037A1 DOUBLE GATE DEVICE HAVING A STRAINED CHANNEL 审中-公开
标题翻译：具有应变通道的双门设备
公开(公告)号：WO2006039037A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/031000
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

6. 发明申请

WO2013021255A1 METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATION PROCESSES USING RECOVERABLE SUBSTRATES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS 审中-公开
标题翻译：使用可恢复基板在3D集成工艺中形成结合的半导体结构的方法和通过这种方法形成的结合的半导体结构
公开(公告)号：WO2013021255A1
公开(公告)日：2013-02-14
申请号：PCT/IB2012/001494
申请日：2012-08-02
申请人： SOITEC , SADAKA, Mariam , NGUYEN, Bich-Yen
发明人： SADAKA, Mariam , NGUYEN, Bich-Yen
IPC分类号： H01L21/683 , H01L25/065 , H01L21/60 , H01L21/768 , H01L23/14 , H01L21/48
CPC分类号： H01L21/6835 , H01L21/76898 , H01L24/03 , H01L24/06 , H01L24/80 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/05009 , H01L2224/05025 , H01L2224/80006 , H01L2224/80095 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06572 , H01L2924/01029 , H01L2924/12041 , H01L2924/12043 , H01L2924/1461 , H01L2924/3511 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
摘要翻译：形成键合的半导体结构的方法包括通过晶片互连通过第一衬底结构的材料层形成，在材料层上结合一个或多个半导体结构，以及将半导体结构与贯穿晶片互连电连接。第二衬底结构可以在与第一衬底结构相对的一侧上结合在经处理的半导体结构上。然后可以去除第一衬底结构的一部分，留下其中附着有经处理的半导体结构的贯穿晶片互连的材料层。然后至少一个贯穿晶片互连可以电耦合到另一结构的导电特征，之后可以去除第二衬底结构。使用这种方法形成结合的半导体结构。

7. 发明申请

WO2007114983A3 METHOD OF MAKING A MULTIPLE CRYSTAL ORIENTATION SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2007114983A3
公开(公告)日：2007-10-11
申请号：PCT/US2007/062793
申请日：2007-02-26
申请人： FREESCALE SEMICONDUCTOR INC. , SADAKA, Mariam, G. , NGUYEN, Bich-Yen , WHITE, Ted, R.
发明人： SADAKA, Mariam, G. , NGUYEN, Bich-Yen , WHITE, Ted, R.
IPC分类号： H01L21/84
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.

8. 发明申请

WO2006103055A1 A METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING AN ARCHED STRUCTURE STRAINED SEMICONDUCTOR LAYER 审中-公开
标题翻译：制造具有结构应变半导体层的半导体器件的方法
公开(公告)号：WO2006103055A1
公开(公告)日：2006-10-05
申请号：PCT/EP2006/002858
申请日：2006-03-29
申请人： PAUL SCHERRER INSTITUT , GARCHING INNOVATIONS GMBH , NGUYEN, Bich-Yen , THOMAS, Shawn, G. , CERGEL, Lubomir , SADAKA, Mariam, G. , THEAN, Voon-Yew , WENNEKERS, Peter , WHITE, Ted, R. , WILD, Andreas, A. , GRUETZMACHER, Detlev , SCHMIDT, Oliver, G.
发明人： NGUYEN, Bich-Yen , THOMAS, Shawn, G. , CERGEL, Lubomir , SADAKA, Mariam, G. , THEAN, Voon-Yew , WENNEKERS, Peter , WHITE, Ted, R. , WILD, Andreas, A. , GRUETZMACHER, Detlev , SCHMIDT, Oliver, G.
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66772 , H01L29/7842 , H01L29/78648 , H01L29/78687
摘要： A method of forming a semiconductor device includes forming a local straininducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.
摘要翻译：形成半导体器件的方法包括在电介质层内的点位置形成第一半导体材料的局部应变致动结构。局部应变诱导结构具有规定的几何形状，其表面设置在电介质层的表面之上。第二半导体材料形成在电介质层和局部应变诱导结构之上，其中第二材料的第一部分在电介质层上的形成提供了第二材料的多晶结构，并且其中形成第二材料的第二部分局部应变诱导结构上的材料提供由局部应变诱导结构的表面经受机械应变的第二材料的单晶结构。单晶结构用作半导体器件的应变半导体层。

9. 发明申请

WO2005034191A2 TEMPLATE LAYER FORMATION 审中-公开
标题翻译：模板层形成
公开(公告)号：WO2005034191A2
公开(公告)日：2005-04-14
申请号：PCT/US2004/030088
申请日：2004-09-14
申请人： FREESCALE SEMICONDUCTOR, INC. , LIU, Chun-Li , SADAKA, Mariam, G. , BARR, Alexander, L. , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn, G. , WHITE, Ted, R. , XIE, Qianghua
发明人： LIU, Chun-Li , SADAKA, Mariam, G. , BARR, Alexander, L. , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn, G. , WHITE, Ted, R. , XIE, Qianghua
IPC分类号： H01L
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

10. 发明申请

WO2006039038A2 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 审中-公开
标题翻译：形成具有应变通道和异常源/漏极的半导体器件的方法
公开(公告)号：WO2006039038A2
公开(公告)日：2006-04-13
申请号：PCT/US2005/031001
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam G. , WHITE, Ted R. , BARR, Alexander L. , KOLAGUNTA, Venkat R. , NGUYEN, Bich-Yen , VARTANIAN, Victor H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam G. , WHITE, Ted R. , BARR, Alexander L. , KOLAGUNTA, Venkat R. , NGUYEN, Bich-Yen , VARTANIAN, Victor H. , ZHANG, Da
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

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