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1. 发明申请

WO2009112894A8 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 审中-公开
公开(公告)号：WO2009112894A8
公开(公告)日：2009-09-17
申请号：PCT/IB2008/052203
申请日：2008-03-13
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
发明人： ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
IPC分类号： H01L29/78
摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 10 10 charges/cm 2 . The invention also relates to a process for making such a substrate.

2. 发明申请

WO2006082247A1 MULTI-GATE FET WITH MULTI-LAYER CHANNEL 审中-公开
标题翻译：具有多层通道的多栅极FET
公开(公告)号：WO2006082247A1
公开(公告)日：2006-08-10
申请号：PCT/EP2006/050691
申请日：2006-02-06
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , AKATSU, Takeshi , GHYSELEN, Bruno
发明人： ALLIBERT, Frédéric , AKATSU, Takeshi , GHYSELEN, Bruno
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66742 , H01L29/7842 , H01L29/78687
摘要： The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarised, where the channel has a multi-layer structure with at least three layers, and with at least one of the layers of the multi-layer structure having electrical properties that are substantially different from those of another layer of the multi-layer structure, characterised in that a single gate or two gates are substantially perpendicular to the reference plane of the channel defined by an interface plane between two layers of the multi-layer structure.
摘要翻译：本发明涉及具有漏极，源极，与源极和漏极电接触的沟道以及至少一个栅极的场效应晶体管，以便在每个栅极极化时向沟道施加电场，其中所述通道具有至少三层的多层结构，并且所述多层结构的所述层中的至少一层具有与所述多层结构的另一层的电性质基本上不同的电特性，其特征在于，单个栅极或两个栅极基本上垂直于由多层结构的两层之间的界面平面限定的沟道的参考平面。

3. 发明申请

WO2009013268A1 CHARGE RESERVOIR STRUCTURE 审中-公开
标题翻译：充电储备结构
公开(公告)号：WO2009013268A1
公开(公告)日：2009-01-29
申请号：PCT/EP2008/059524
申请日：2008-07-21
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , KERDILES, Sébastien
发明人： ALLIBERT, Frédéric , KERDILES, Sébastien
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/02126 , H01L21/02164 , H01L21/02321 , H01L21/0234 , H01L21/02343 , H01L21/28282 , H01L21/31612 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645
摘要： The present invention relates to a production process of a semiconductor on insulator type structure comprising a semiconductor layer (11) of a donor substrate (10), an insulator layer (60) and a receiver substrate (20), the process comprising the bonding of the donor substrate (10) on the receiver substrate (20), at least one of the substrates being coated with an insulator layer, characterised in that it comprises the formation at the bonding interface of a so-called trapping interface (30) comprising electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor on insulator type structure comprising a trapping interface.
摘要翻译：本发明涉及一种半导体绝缘体型结构的制造方法，其包括施主衬底（10）的半导体层（11），绝缘体层（60）和接收衬底（20），该工艺包括：在所述接收器基板（20）上的所述施主衬底（10）上，所述衬底中的至少一个涂覆有绝缘体层，其特征在于，其包括在所谓的捕集界面（30）的键合界面处的形成，适用于保留电荷载体的主动阱。本发明还涉及包括捕获接口的半导体绝缘体型结构。

4. 发明申请

WO2008116879A1 PROCESS FOR MANUFACTURING A COMPOSITE SUBSTRATE 审中-公开
标题翻译：制造复合基板的方法
公开(公告)号：WO2008116879A1
公开(公告)日：2008-10-02
申请号：PCT/EP2008/053563
申请日：2008-03-26
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , KERDILES, Sébastien
发明人： ALLIBERT, Frédéric , KERDILES, Sébastien
IPC分类号： H01L21/762 , H01L21/68
CPC分类号： H01L21/76254 , H01L24/27 , H01L24/33 , H01L2221/68318 , H01L2221/68368 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01032 , H01L2924/01033 , H01L2924/01058 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/3512 , H01L2924/00
摘要： The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate (10) onto a second semi-conducting substrate (30), characterised in that it includes, before bonding, the formation of a bonding layer (20) between the first and the second substrate, said bonding layer (20) comprising a plurality of islands (21) distributed over the surface of the first substrate (10) in a determined pattern and separated from one another by regions (22) of a different type, which are distributed in a complementary pattern, wherein said islands (21) are formed via a plasma treatment of the material of the first substrate (10).
摘要翻译：本发明涉及一种用于制造复合衬底的方法，包括将第一衬底（10）接合到第二半导电衬底（30）上，其特征在于，其在接合之前包括在第二半导电衬底（30）之间形成结合层（20）第一和第二衬底，所述接合层（20）包括以确定的图案分布在第一衬底（10）的表面上的多个岛（21），并且通过不同类型的区域（22）彼此分离，其以互补图案分布，其中通过等离子体处理第一基板（10）的材料形成所述岛（21）。

5. 发明申请

WO2005088716A2 TREATMENT METHOD AND DEVICE OF THE WORKING LAYER OF A MULTILAYER STRUCTURE 审中-公开
标题翻译：多层结构工作层的处理方法和装置
公开(公告)号：WO2005088716A2
公开(公告)日：2005-09-22
申请号：PCT/IB2005/000832
申请日：2005-03-10
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , BRUNIER, François
发明人： ALLIBERT, Frédéric , BRUNIER, François
IPC分类号： H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： According to a first embodiment, the invention relates to a method for treating an electrically conductive working layer of a multilayer structure made from semiconductor materials, the structure including under said working layer an electrically insulating layer, said treatment being destined to constitute in said working layer at least one island surrounded by material of the electrically insulating layer, method including a wet chemical etching step of the working layer, method characterised in that prior to the wet etching step selective masking is realised on several regions of said working layer in order to constitute in this working layer several islands, each region masked from the layer corresponding to a respective island. The invention also proposes the application of such a method to the characterisation of the electrical properties of a structure, and an associated device.
摘要翻译：根据第一实施例，本发明涉及一种用于处理由半导体材料制成的多层结构的导电工作层的方法，所述结构包括在所述工作层下方的电绝缘层，所述处理旨在构成在所述工作层由电绝缘层的材料包围的至少一个岛，包括工作层的湿化学蚀刻步骤的方法，其特征在于，在湿蚀刻步骤之前，在所述工作层的几个区域上实现选择性掩蔽以构成在该工作层中，几个岛，每个区域从对应于相应岛的层掩蔽。本发明还提出了这种方法用于表征结构和相关联的装置的电气特性的应用。

6. 发明公开

EP2174347A1 CHARGE RESERVOIR STRUCTURE 审中-公开
标题翻译： CARGO库结构
公开(公告)号：EP2174347A1
公开(公告)日：2010-04-14
申请号：EP08775250.7
申请日：2008-07-21
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： ALLIBERT, Frédéric , KERDILES, Sébastien
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/02126 , H01L21/02164 , H01L21/02321 , H01L21/0234 , H01L21/02343 , H01L21/28282 , H01L21/31612 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645
摘要： The present invention relates to a production process of a semiconductor on insulator type structure comprising a semiconductor layer (11) of a donor substrate (10), an insulator layer (60) and a receiver substrate (20), the process comprising the bonding of the donor substrate (10) on the receiver substrate (20), at least one of the substrates being coated with an insulator layer, characterised in that it comprises the formation at the bonding interface of a so-called trapping interface (30) comprising electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor on insulator type structure comprising a trapping interface.

7. 发明公开

EP1949430A1 TRAITEMENT D'UNE COUCHE DE GERMANIUM COLLEE A UN SUBSTRAT 审中-公开
标题翻译：治疗A SUBSTRATE粘结锗层
公开(公告)号：EP1949430A1
公开(公告)日：2008-07-30
申请号：EP06820227.4
申请日：2006-10-17
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： ALLIBERT, Frédéric , DEGUET, Chrystel , RICHTARCH, Claire
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： The invention concerns a method for treating a structure comprising a thin Ge layer on a substrate, said layer having been previously bonded to the substrate, the method including a treatment for improving the electrical properties of the layer and/or of the interface of the Ge layer with the underlying layer. The invention is characterized in that said treatment is a heat treatment implemented at a temperature ranging between 5000C and 6000C for a maximum of 3 hours. The invention also concerns a method for producing a structure comprising a Ge layer, the method including bonding a donor substrate comprising at least in its upper part a thin Ge layer and a receiver substrate, characterized in that it includes the following steps: (a) bonding the donor substrate to the receiver substrate such that the Ge layer is located in the neighborhood of the bonding interface; (b) eliminating part of the donor substrate not including the Ge layer; (c) treating the structure comprising the receiver substrate and the Ge layer in accordance with the treatment method.

8. 发明公开

EP1723671A2 TREATMENT METHOD AND DEVICE OF THE WORKING LAYER OF A MULTILAYER STRUCTURE 审中-公开
标题翻译：面粉AGEN结构的主动层处理方法及装置
公开(公告)号：EP1723671A2
公开(公告)日：2006-11-22
申请号：EP05708800.7
申请日：2005-03-10
申请人： S.O.I.TEC. Silicon on Insulator Technologies S.A.
发明人： ALLIBERT, Frédéric , BRUNIER, François
IPC分类号： H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： According to a first embodiment, the invention relates to a method for treating an electrically conductive working layer of a multilayer structure made from semiconductor materials, the structure including under said working layer an electrically insulating layer, said treatment being destined to constitute in said working layer at least one island surrounded by material of the electrically insulating layer, method including a wet chemical etching step of the working layer, method characterised in that prior to the wet etching step selective masking is realised on several regions of said working layer in order to constitute in this working layer several islands, each region masked from the layer corresponding to a respective island. The invention also proposes the application of such a method to the characterisation of the electrical properties of a structure, and an associated device.

9. 发明公开

EP2269226A1 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 审中-公开
标题翻译：与载样基材在区域查出的埋层
公开(公告)号：EP2269226A1
公开(公告)日：2011-01-05
申请号：EP08763204.8
申请日：2008-03-13
申请人： S.O.I.Tec Silicon on Insulator Technologies
发明人： ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
IPC分类号： H01L29/78
CPC分类号： H01L29/78603 , H01L29/32 , H01L29/7841 , H01L31/0248
摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 10
10 charges/cm
2 . The invention also relates to a process for making such a substrate.

10. 发明申请

WO2007045759A1 TRAITEMENT D'UNE COUCHE DE GERMANIUM COLLEE A UN SUBSTRAT 审中-公开
标题翻译：处理粘结到基材上的锗层
公开(公告)号：WO2007045759A1
公开(公告)日：2007-04-26
申请号：PCT/FR2006/002332
申请日：2006-10-17
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , DEGUET, Chrystel , RICHTARCH, Claire
发明人： ALLIBERT, Frédéric , DEGUET, Chrystel , RICHTARCH, Claire
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： L'invention concerne un procédé de traitement d'une structure comprenant une couche mince de Ge sur un substrat, ladite couche ayant été préalablement collée au substrat, le procédé comprenant un traitement pour améliorer les propriétés électriques de la couche et/ou de l'interface de la couche de Ge avec la couche sous-jacente, caractérisé en ce que ledit traitement est un traitement thermique mis en œuvre à une température comprise entre 5000C et 6000C pendant au maximum 3 heures. L'invention concerne aussi un procédé de réalisation d'une structure comprenant une couche de Ge, le procédé comprenant un collage entre un substrat donneur comportant au moins dans sa partie supérieure une couche mince de Ge et un substrat récepteur, caractérisé en ce qu'il comprend les étapes suivantes : (a) collage du substrat donneur au substrat récepteur de sorte que la couche de Ge se trouve au voisinage de l'interface de collage ; (b) retrait de la partie du substrat donneur ne comprenant pas la couche de Ge ; (c) traitement de la structure comprenant le substrat récepteur et la couche de Ge conformément audit procédé de traitement.
摘要翻译：本发明涉及一种用于处理在衬底上包括薄Ge层的结构的方法，所述层已经预先结合到衬底上，该方法包括用于改善Ge层和/或Ge界面的电性能的处理层与底层。本发明的特征在于，所述处理是在500℃至600℃之间的温度下实施最多3小时的热处理。本发明还涉及一种用于制造包括Ge层的结构的方法，所述方法包括将包括至少在其上部的薄Ge层和接收衬底的施主衬底结合，其特征在于，其包括以下步骤：（a）将施主衬底接合到接收器衬底，使得Ge层位于接合界面附近; （b）消除不包括Ge层的供体衬底的一部分; （c）根据处理方法处理包括接收器基板和Ge层的结构。

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