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1. 发明授权

US07145366B2 Electronic circuit with a differential pair of transistors and logic gate comprising such a circuit 有权
标题翻译：具有差分对晶体管和包含这种电路的逻辑门的电子电路
公开(公告)号：US07145366B2
公开(公告)日：2006-12-05
申请号：US10954619
申请日：2004-09-30
申请人： Sébastien Rieubon , Serge Ramet , Philippe Level
发明人： Sébastien Rieubon , Serge Ramet , Philippe Level
IPC分类号： H03K19/086 , H03K19/20
CPC分类号： H03K17/04166 , H03K17/04113 , H03K19/0136 , H03K19/086
摘要： An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.
摘要翻译：电子电路包括至少一个差分对晶体管，控制晶体管开关，第一电流源和第二电流源。第二电流源连接到一对晶体管的公共发射极节点，以便在开关操作期间加速寄生电容的放电。

2. 发明授权

US06822520B2 Low noise load pump for phase-locking loop 有权
标题翻译：用于锁相环的低噪声负载泵
公开(公告)号：US06822520B2
公开(公告)日：2004-11-23
申请号：US10204170
申请日：2002-10-15
申请人： Serge Ramet , Sébastien Rieubon
发明人： Serge Ramet , Sébastien Rieubon
IPC分类号： H03L706
CPC分类号： H03L7/0896 , H03L7/18
摘要： The invention concerns a load pump for phase-locking loop comprising a first current source (14), a second current source (16), several switches (M1, M2, M3, M4) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means (18) adapted to store a physical quantity corresponding to the value of the current (11) supplied by the first current source (14), so that the value of the current (12) supplied by the second current source is substantially equal to the value of current (11) supplied by the first current source.
摘要翻译：本发明涉及一种用于锁相环的负载泵，包括第一电流源（14），第二电流源（16），适于传送第一和/或第二电流的多个开关（M1，M2，M3，M4）源与负载泵输出（OUT）。第二电流源由适于存储对应于由第一电流源（14）提供的电流（11）的值的物理量的控制装置（18）驱动，使得由第二电流源基本上等于由第一电流源提供的电流（11）的值。

3. 发明申请

US20120229185A1 Time-to-Digital Converter with Successive Measurements 审中-公开
标题翻译：具有连续测量的时间 - 数字转换器
公开(公告)号：US20120229185A1
公开(公告)日：2012-09-13
申请号：US13509346
申请日：2010-11-12
申请人： Sébastien Rieubon
发明人： Sébastien Rieubon
IPC分类号： H03L7/08 , H03M1/50
CPC分类号： H03K5/159
摘要： The invention relates to the conversion into digital information of the time difference between a first signal and a second signal. In particular, in order to determine a fractional part of the number of periods of a first signal for a period of a second signal, the following are alternately performed: /1/ delaying the second signal relative to the first signal and determining a first digital information item, a function of the fractional part, /2/ delaying the first signal relative to the second signal and determining a second digital information item, a function of the fractional part. Then the fractional part is calculated as a function of the previously obtained first and second digital information items.
摘要翻译：本发明涉及将第一信号和第二信号之间的时间差转换为数字信息。具体地，为了确定第二信号的周期中的第一信号的周期数的分数部分，交替执行以下操作：/ 1 /相对于第一信号延迟第二信号并确定第一数字信息项，分数部分的函数，/ 2 /相对于第二信号延迟第一信号，并确定第二数字信息项，分数部分的函数。然后根据先前获得的第一和第二数字信息项的函数计算小数部分。

4. 发明授权

US06680628B2 Method and device for frequency synthesis using a phase locked loop 失效
标题翻译：使用锁相环进行频率合成的方法和装置
公开(公告)号：US06680628B2
公开(公告)日：2004-01-20
申请号：US10069444
申请日：2002-05-22
申请人： Arnaud Brunet , Sébastien Rieubon
发明人： Arnaud Brunet , Sébastien Rieubon
IPC分类号： H03B2100
CPC分类号： H03L7/1974 , H03L7/0891 , H03L7/1972
摘要： A frequency synthesis method using a phase locked loop including a phase comparator. The method includes switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of the loop has elapsed. The method is characterized in that it consists of effecting the operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).
摘要翻译：一种使用包括相位比较器的锁相环的频率合成方法。该方法包括在经过了用于稳定循环的操作的时间或时间延迟之后从分数分频操作模式切换到整数分频操作模式。该方法的特征在于，它包括通过在施加到相位比较器（3）的输入之前通过掩蔽或消除参考信号（Sref）和比较信号（Scomp）的脉冲的一部分来实现操作模式切换，。

5. 发明授权

US08212597B2 Method for detecting the locking of a phase-locked loop and associated device 有权
标题翻译：用于检测锁相环和相关装置的锁定的方法
公开(公告)号：US08212597B2
公开(公告)日：2012-07-03
申请号：US12688098
申请日：2010-01-15
申请人： Michael Kraemer , Sébastien Rieubon
发明人： Michael Kraemer , Sébastien Rieubon
IPC分类号： H03L7/06
CPC分类号： H04L7/0331 , H03L7/095 , H04L7/033
摘要： A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.
摘要翻译：一种用于检测产生输出信号的锁相环的锁定的方法，包括基于输出信号作为输入接收参考信号和第二信号的相位比较器。产生具有基于输出信号的第三信号的至少两个周期的持续时间并且位于第二信号的有效负载边缘周围的时间窗口。执行在第二信号的有效载荷边缘的时间窗内和第一侧的第三信号的第一有效载荷边缘处的参考信号和第二信号的第一比较。然后，执行第二信号的有效载荷边缘的时间窗内和第二侧的第三信号的第二有效载荷边缘处的参考信号和第二信号的第二比较。检测在第一和第二比较期间基于参考信号和第二信号相等的锁相环的锁定。

6. 发明授权

US07466789B2 Counter with correction circuitry 有权
标题翻译：带校正电路的计数器
公开(公告)号：US07466789B2
公开(公告)日：2008-12-16
申请号：US11724517
申请日：2007-03-15
申请人： Sébastien Rieubon , Michael Kraemer
发明人： Sébastien Rieubon , Michael Kraemer
IPC分类号： H03K25/00 , H03K9/06 , H03D3/00
CPC分类号： H03K21/406
摘要： The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.
摘要翻译：本发明涉及用于基于在参考时间段期间发生的输入信号的上升沿和下降沿的数量来提供经校正的计数值的计数电路，该计数电路包括一个计数器，该计数器被布置为基于数字中的一个提供第一计数值在参考时间段期间发生的输入信号的上升沿和在参考时间段期间发生的输入信号的下降沿的数量; 其中所述计数电路还包括调整电路，所述调整电路被布置成通过在所述参考时间段的开始时间和结束时间确定所述输入信号的状态来产生校正的计数值，以及如果所述输入信号的状态在参考时间段的开始与参考时间段结束时的输入信号的状态不同。

7. 发明申请

US20100176845A1 METHOD FOR DETECTING THE LOCKING OF A PHASE-LOCKED LOOP AND ASSOCIATED DEVICE 有权
标题翻译：用于检测相位锁定环路和相关设备的锁定的方法
公开(公告)号：US20100176845A1
公开(公告)日：2010-07-15
申请号：US12688098
申请日：2010-01-15
申请人： Michael KRAEMER , Sébastien Rieubon
发明人： Michael KRAEMER , Sébastien Rieubon
IPC分类号： H03D13/00
CPC分类号： H04L7/0331 , H03L7/095 , H04L7/033
摘要： A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.
摘要翻译：一种用于检测产生输出信号的锁相环的锁定的方法，包括基于输出信号作为输入接收参考信号和第二信号的相位比较器。产生具有基于输出信号的第三信号的至少两个周期的持续时间并且位于第二信号的有效负载边缘周围的时间窗口。执行在第二信号的有效载荷边缘的时间窗内和第一侧的第三信号的第一有效载荷边缘处的参考信号和第二信号的第一比较。然后，执行第二信号的有效载荷边缘的时间窗内和第二侧的第三信号的第二有效载荷边缘处的参考信号和第二信号的第二比较。检测在第一和第二比较期间基于参考信号和第二信号相等的锁相环的锁定。

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