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1. 发明授权

US07111029B2 Random number generating circuit 失效
公开(公告)号：US07111029B2
公开(公告)日：2006-09-19
申请号：US10235827
申请日：2002-09-06
申请人： Shinobu Fujita , Ken Uchida , Ryuji Ohba , Junji Koga
发明人： Shinobu Fujita , Ken Uchida , Ryuji Ohba , Junji Koga
IPC分类号： G06F1/02
CPC分类号： H04L9/0861 , G06F7/588
摘要： A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

2. 发明授权

US06690030B2 Semiconductor device with negative differential resistance characteristics 失效
标题翻译：具有负差分电阻特性的半导体器件
公开(公告)号：US06690030B2
公开(公告)日：2004-02-10
申请号：US09798923
申请日：2001-03-06
申请人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
发明人： Junji Koga , Ken Uchida , Ryuji Ohba , Akira Toriumi
IPC分类号： H01L2940
CPC分类号： H01L27/1104 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/511 , H01L29/7881
摘要： A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.
摘要翻译：形成在硅衬底表面上的栅极氧化膜的厚度部分地减小或者在其源区域上的指定部分“薄化”。在栅极区域中，以层叠的顺序形成包括p型导电体的第一多晶硅或“多晶硅”膜，隧道氧化物膜和第二p型多晶硅膜的多层结构。源极区域和第一多晶硅膜构成了高浓度杂质掺杂的pn结，其间铺设有薄的氧化硅膜，提供了也称为Esaki二极管的隧道二极管。二极管用于负差分电阻。此外，第一和第二多晶硅膜之间的部分是用作负载的非线性隧道电阻器。负的差分电阻和负载在低压电源（接地电位）Vss和高压电源Vdd之间串联连接在一起，从而能够形成具有内置双稳态电路的晶体管。读取用作数据存储节点的第一多晶硅膜的电位信息，并施加晶体管放大。因此，高速执行数据读取。同时，在电源之间流动的电流被抑制到较低的电平，从而使等待模式中的功耗最小化。

3. 发明授权

US07138651B2 Logic apparatus and logic circuit 有权
公开(公告)号：US07138651B2
公开(公告)日：2006-11-21
申请号：US10893916
申请日：2004-07-20
申请人： Ken Uchida , Junji Koga , Ryuji Ohba
发明人： Ken Uchida , Junji Koga , Ryuji Ohba
IPC分类号： H01L29/06
CPC分类号： B82Y10/00 , H01L29/7888 , H01L49/006 , H03K19/08
摘要： A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

4. 发明授权

US06787795B2 Logic apparatus and logic circuit 有权
标题翻译：逻辑设备和逻辑电路
公开(公告)号：US06787795B2
公开(公告)日：2004-09-07
申请号：US09990362
申请日：2001-11-23
申请人： Ken Uchida , Junji Koga , Ryuji Ohba
发明人： Ken Uchida , Junji Koga , Ryuji Ohba
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L29/7888 , H01L49/006 , H03K19/08
摘要： A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.
摘要翻译：具有串联或并联连接的第一和第二单电子器件的逻辑器件。每个单电子器件包括绝缘地设置在两个隧道势垒之间的导电岛，其将导电岛与相应的源/漏电极分离。第一电荷存储区分别绝缘地设置在导电岛和栅电极之上和之下。当在电荷存储区域中累积电荷时，各器件的库仑振荡从库仑振荡偏移了半周期，当没有电荷累积时产生库仑振荡。

5. 发明授权

US06680505B2 Semiconductor storage element 有权
标题翻译：半导体存储元件
公开(公告)号：US06680505B2
公开(公告)日：2004-01-20
申请号：US10107440
申请日：2002-03-28
申请人： Ryuji Ohba , Junji Koga , Ken Uchida
发明人： Ryuji Ohba , Junji Koga , Ken Uchida
IPC分类号： H01L2972
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/7883
摘要： A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and second tunnel insulator layers formed over the channel region and through which electrons can directly tunnel quantum-mechanically; and a conductive particle layer which is sandwiched in between the first and second tunnel insulator layers; the charge stored layer being formed on the second tunnel insulator layer. An energy level at which the information electron in the charge stored layer is injected is lower than the energy level of a conduction band edge in the channel region.
摘要翻译：一种具有电荷存储层作为浮动栅极并且其存储时间足够长的非易失性半导体存储元件。存储元件包括形成在源极区域和漏极区域之间的沟道区域; 形成在通道区域上的第一和第二隧道绝缘体层，电子可以通过其直接隧道量子力学; 以及夹在所述第一和第二隧道绝缘体层之间的导电性粒子层; 电荷存储层形成在第二隧道绝缘体层上。注入电荷存储层中的信息电子的能级低于沟道区的导带边缘的能级。

6. 发明申请

US20120061746A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20120061746A1
公开(公告)日：2012-03-15
申请号：US13225025
申请日：2011-09-02
申请人： Ryuji Ohba
发明人： Ryuji Ohba
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/4234
摘要： According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value ΔE1 required for charging one electron in the first conductive nanoparticle is smaller than an average energy value ΔE required for charging one electron in the second conductive nanoparticle, and a difference between ΔE1 and ΔE is larger than a heat fluctuation energy (kBT).
摘要翻译：根据一个实施例，在形成在半导体衬底的沟道区上的隧道绝缘膜上形成电荷存储层的非易失性半导体存储器中，在沟道侧形成含有第一导电纳米颗粒的第一纳米颗粒层，在电荷存储层侧形成含有平均粒径大于第一导电性纳米粒子的多个第二导电性纳米粒子的第二纳米粒子层。在第一导电纳米颗粒中对一个电子充电所需的平均能量值＆Dgr; E1小于在第二导电纳米颗粒中对一个电子进行充电所需的平均能量值＆Dgr; E，并且Dgr; E1和＆Dgr之间的差异为大于热波动能（kBT）。

7. 发明申请

US20070296025A1 RANDOM NUMBER GENERATING DEVICE 有权
标题翻译：随机数生成装置
公开(公告)号：US20070296025A1
公开(公告)日：2007-12-27
申请号：US11743265
申请日：2007-05-02
申请人： Mari Matsumoto , Ryuji Ohba , Shinobu Fujita
发明人： Mari Matsumoto , Ryuji Ohba , Shinobu Fujita
IPC分类号： H01L29/792
CPC分类号： G06F7/588 , H03B29/00
摘要： A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Six(SiO2)y(Si3N4)1-yMz (M is an element other than Si, O, and N, x≧0, 1≧y≧0, z≧0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.
摘要翻译：随机数发生装置包括：半导体器件，包括源区域，漏极区域，设置在源极区域和漏极区域之间的沟道区域;以及绝缘部分，设置在沟道区域上，绝缘部分包括捕获绝缘膜，基于悬挂键并由Si x Si（SiO 2）y（Si 3 N）3表示的陷阱（M是除Si，O和N之外的元素，x> = 0,1，= y> = 0，z> = 0，x = 0且y = 1，z = 0的情况除外），根据陷阱中捕获的电荷量随机地变化的信道区域的导电率和连接的随机数发生单元并且基于沟道区域的导电性的随机变化产生随机数。

8. 发明授权

US08587050B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08587050B2
公开(公告)日：2013-11-19
申请号：US13419930
申请日：2012-03-14
申请人： Ryuji Ohba
发明人： Ryuji Ohba
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , G11C2216/06 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, there is provided a semiconductor memory that includes: a semiconductor substrate having a channel region; a first tunnel insulating film on the channel region; a first fine particle layer on the first tunnel insulating film, the first fine particle layer including first conductive fine particles; a second tunnel insulating film on the first fine particle layer; a second fine particle layer on the second tunnel insulating film, the second fine particle layer including second conductive fine particles; a third tunnel insulating film on the second fine particle layer; a third fine particle layer on the third tunnel insulating film, the third fine particle layer including third conductive fine particles. A mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles and that of the third conductive fine particles.
摘要翻译：在一个实施例中，提供一种半导体存储器，其包括：具有沟道区的半导体衬底; 在通道区域上的第一隧道绝缘膜; 所述第一隧道绝缘膜上的第一细颗粒层，所述第一细颗粒层包括第一导电细颗粒; 在第一细颗粒层上的第二隧道绝缘膜; 在第二隧道绝缘膜上的第二细颗粒层，第二微粒层包括第二导电细颗粒; 第二细颗粒层上的第三隧道绝缘膜; 第三隧道绝缘膜上的第三细颗粒层，第三细颗粒层包括第三导电细颗粒。第二导电性微粒的平均粒径大于第一导电性微粒和第三导电性微粒的平均粒径。

9. 发明授权

US08307022B2 Random number generating device 有权
标题翻译：随机数生成装置
公开(公告)号：US08307022B2
公开(公告)日：2012-11-06
申请号：US12130567
申请日：2008-05-30
申请人： Mari Matsumoto , Ryuji Ohba , Shinichi Yasuda , Shinobu Fujita
发明人： Mari Matsumoto , Ryuji Ohba , Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , H03K3/84
摘要： A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.
摘要翻译：随机数生成装置包括：脉冲电压发生器，被配置为产生具有26mV或更大幅度的脉冲电压; 包括形成在半导体衬底上彼此间隔一定距离的源极和漏极区域的随机噪声产生元件，形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的隧道绝缘膜以及形成在栅极电极上的栅电极隧道绝缘膜，并且施加脉冲电压，所述随机噪声产生元件被配置为产生包含在源极区域和漏极区域之间的电流中的随机噪声; 以及随机数生成单元，被配置为基于随机噪声生成随机数信号。

10. 发明授权

US08115248B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08115248B2
公开(公告)日：2012-02-14
申请号：US12388966
申请日：2009-02-19
申请人： Tetsuya Kai , Ryuji Ohba , Yoshio Ozawa
发明人： Tetsuya Kai , Ryuji Ohba , Yoshio Ozawa
IPC分类号： H01L21/331
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11521 , H01L29/42332 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括设置在所述半导体衬底的表面上的隧道绝缘膜，所述隧道绝缘膜包括半导体晶粒，所述半导体晶粒包括在隧道绝缘膜的两端部比隧道绝缘膜的其他部分所包含的半导体晶粒小的晶粒尺寸，隧道绝缘膜上设置的电荷存储层，设置在电荷存储层上的绝缘膜，以及控制栅电极设置在绝缘膜上。

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