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1. 发明授权

US08524592B1 Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices 有权
标题翻译：形成具有自对准触点和低k间隔物的半导体器件的方法以及所得到的器件
公开(公告)号：US08524592B1
公开(公告)日：2013-09-03
申请号：US13584055
申请日：2012-08-13
申请人： Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/78 , H01L21/76897 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.
摘要翻译：本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层间隙填充材料并形成邻近衬层的低k侧壁间隔物。还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

2. 发明授权

US08541274B1 Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation 有权
标题翻译：形成具有纳米线栅极结构的三维半导体器件的方法，其中在源极/漏极形成之后形成纳米线栅极结构
公开(公告)号：US08541274B1
公开(公告)日：2013-09-24
申请号：US13609828
申请日：2012-09-11
申请人： Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L21/845 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/78696
摘要： In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.
摘要翻译：在一个实例中，本文公开的方法包括形成由半导体材料构成的鳍片，其中鳍片具有第一成形截面构造，在鳍片之上形成牺牲栅极结构，形成邻近至少一部分的侧壁间隔物的牺牲栅极结构，并且去除牺牲栅极结构，从而限定暴露鳍片的一部分的栅极腔。该方法还包括以下步骤：在鳍的暴露部分上执行翅片回流处理以限定具有与第一截面构造不同的横截面构造的纳米线结构，并在栅腔中形成替代栅极结构并且至少部分地围绕纳米线结构。

3. 发明申请

US20140035010A1 INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有替代盖结构的集成电路及其制造方法
公开(公告)号：US20140035010A1
公开(公告)日：2014-02-06
申请号：US13562659
申请日：2012-07-31
申请人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
发明人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L21/76834 , H01L21/28518 , H01L21/76897 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.
摘要翻译：一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

4. 发明授权

US08748309B2 Integrated circuits with improved gate uniformity and methods for fabricating same 有权
标题翻译：具有改善的栅极均匀性的集成电路及其制造方法
公开(公告)号：US08748309B2
公开(公告)日：2014-06-10
申请号：US13618035
申请日：2012-09-14
申请人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/44
CPC分类号： H01L29/4958 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L29/4966 , H01L29/66545
摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.
摘要翻译：提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。第一区域由第一材料形成，第二区域由第二材料形成。在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。被照射的层被蚀刻以形成凹部。

5. 发明授权

US08735272B2 Integrated circuit having a replacement gate structure and method for fabricating the same 有权
标题翻译：具有替代栅极结构的集成电路及其制造方法
公开(公告)号：US08735272B2
公开(公告)日：2014-05-27
申请号：US13562659
申请日：2012-07-31
申请人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
发明人： Xiuyu Cai , Ruilong Xie , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/28518 , H01L21/76897 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.
摘要翻译：一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

6. 发明申请

US20140077274A1 INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有改进的门盖均匀性的集成电路及其制造方法
公开(公告)号：US20140077274A1
公开(公告)日：2014-03-20
申请号：US13618035
申请日：2012-09-14
申请人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L29/78 , H01L21/425
CPC分类号： H01L29/4958 , H01L21/28088 , H01L21/32134 , H01L21/32135 , H01L29/4966 , H01L29/66545
摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.
摘要翻译：提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。第一区域由第一材料形成，第二区域由第二材料形成。在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。被照射的层被蚀刻以形成凹部。

7. 发明授权

US08580634B1 Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed prior to source/drain formation 有权
标题翻译：形成具有纳米线栅极结构的三维半导体器件的方法，其中在源极/漏极形成之前形成纳米线栅极结构
公开(公告)号：US08580634B1
公开(公告)日：2013-11-12
申请号：US13609941
申请日：2012-09-11
申请人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/42392
摘要： In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a patterned hard mask above the fin, wherein the patterned hard mask has an opening that exposes a portion of the fin, performing a fin reflow process through the opening in the patterned hard mask on the exposed portion of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration, and forming a gate structure that extends at least partially around the nanowire structure.
摘要翻译：在一个示例中，本文公开的方法包括形成由半导体材料构成的鳍片，其中鳍片具有第一成形截面构造，在鳍片之上形成图案化的硬掩模，其中图案化的硬掩模具有开口其暴露所述翅片的一部分，通过所述翅片的暴露部分上的所述图案化硬掩模中的开口进行翅片回流处理，以限定具有不同于所述第一横截面构造的横截面构造的纳米线结构，以及形成至少部分地围绕纳米线结构延伸的栅极结构。

8. 发明授权

US08691696B2 Methods for forming an integrated circuit with straightened recess profile 有权
标题翻译：用于形成具有拉直凹槽轮廓的集成电路的方法
公开(公告)号：US08691696B2
公开(公告)日：2014-04-08
申请号：US13476860
申请日：2012-05-21
申请人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John Iacoponi
发明人： Xiuyu Cai , Xunyuan Zhang , Ruilong Xie , Errol T. Ryan , John Iacoponi
IPC分类号： H01L21/311
CPC分类号： H01L21/311 , H01L21/3105 , H01L21/31116 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76831 , H01L29/66545
摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.
摘要翻译：为形成集成电路提供了方法。在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。侧壁间隔件形成在牺牲心轴的相邻侧壁处。侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。侧壁间隔物还具有与基底基板间隔开的上部。上部具有倾斜的外表面。第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。凹槽的重新设计简洁直观。

9. 发明授权

US08679968B2 Method for forming a self-aligned contact opening by a lateral etch 有权
标题翻译：通过横向蚀刻形成自对准接触开口的方法
公开(公告)号：US08679968B2
公开(公告)日：2014-03-25
申请号：US13471846
申请日：2012-05-15
申请人： Ruilong Xie , Su Chen Fan , Pranatharthiharan Haran Balasubramanian , David Vaclav Horak , Ponoth Shom
发明人： Ruilong Xie , Su Chen Fan , Pranatharthiharan Haran Balasubramanian , David Vaclav Horak , Ponoth Shom
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/823475 , H01L21/76897
摘要： A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the two gate stacks, and laterally removing ILD between the two gate stacks from the vertical contact opening toward the spacers, to form a contact hole.
摘要翻译：描述了没有间隔物或盖损失的自对准源极/漏极接触形成过程。实施例包括提供两个栅极堆叠，每个栅极堆叠在相对的两侧具有间隔物，以及位于两个栅极堆叠之间并在它们之间的空间中的层间电介质（ILD），在两个栅极堆叠之间的ILD内形成垂直接触开口，并横向移除ILD 在两个栅极堆叠之间从垂直接触开口朝向间隔件，形成接触孔。

10. 发明申请

US20140070285A1 METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES 有权
标题翻译：用自对准接触形成半导体器件的方法和结果器件
公开(公告)号：US20140070285A1
公开(公告)日：2014-03-13
申请号：US13611652
申请日：2012-09-12
申请人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
发明人： Ruilong Xie , Ponoth Shom , Xiuyu Cai , Balasubramanian Pranatharthiharan , Robert J. Miller
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636
摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.
摘要翻译：一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层，暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

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