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1. 发明授权

US5877523A Multi-level split- gate flash memory cell 失效
标题翻译：多级分闸闪存单元
公开(公告)号：US5877523A
公开(公告)日：1999-03-02
申请号：US974459
申请日：1997-11-20
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： G11C11/56 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L21/28273 , H01L29/66825 , H01L29/7887 , G11C2211/5612
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

2. 发明授权

US5714412A Multi-level, split-gate, flash memory cell and method of manufacture thereof 失效
标题翻译：多级，分裂门，闪存单元及其制造方法
公开(公告)号：US5714412A
公开(公告)日：1998-02-03
申请号：US755868
申请日：1996-12-02
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： G11C11/56 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788 , H01L21/8247
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L21/28273 , H01L29/66825 , H01L29/7887 , G11C2211/5612
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

3. 发明授权

US6054348A Self-aligned source process 失效
标题翻译：自对准源程序
公开(公告)号：US6054348A
公开(公告)日：2000-04-25
申请号：US79880
申请日：1998-05-15
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L27/11519 , H01L27/11521 , H01L29/66659
摘要： A process for creating a semiconductor memory device, featuring the formation of FOX regions, after the creation of a source region, has been developed. The process features a source region, self-aligned to a first set of stacked gate structures, with the subsequent FOX region placed perpendicular to the source region, between a second set of stacked gate structures.
摘要翻译：已经开发了在创建源区域之后形成FOX区域的半导体存储器件的制造工艺。该过程的特征在于源区域与第一组堆叠的栅极结构自对准，随后的FOX区域垂直于源区域放置在第二组堆叠栅极结构之间。

4. 发明授权

US5851881A Method of making monos flash memory for multi-level logic 失效
标题翻译：制作多级逻辑闪存的方法
公开(公告)号：US5851881A
公开(公告)日：1998-12-22
申请号：US944500
申请日：1997-10-06
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： G11C11/56 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7887 , G11C11/5621 , G11C11/5671 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/7923
摘要： The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.
摘要翻译：本发明提供一种制造分闸门MONOS多电平逻辑存储器件的结构和方法。存储器件具有与MONOS晶体管24A串联的多晶硅栅极晶体管20A。该器件具有实现多级存储器存储（例如，4个电压状态）的新颖操作。该方法通过在半导体衬底10的表面上形成隧道氧化物层30开始。衬底在有源区域中具有堆叠的栅极沟道区域20和MONOS沟道区域24。在堆叠的栅极沟道区域20上形成多晶硅栅极32.在MONOS沟道区24上方，在浮置栅极32和隧道氧化物层上形成具有存储氮化物层的ONO层。形成控制栅电极44 在跨越多晶硅浮栅32和MONOS沟道区24的ONO层41之上。源/漏区50 51形成在衬底中。多晶硅闪光晶体管20A和MONOS闪存晶体管24A组合形成本发明的4电平逻辑存储单元。

5. 发明授权

US5679591A Method of making raised-bitline contactless trenched flash memory cell 失效
标题翻译：制造凸起位线非接触式沟槽闪存单元的方法
公开(公告)号：US5679591A
公开(公告)日：1997-10-21
申请号：US766079
申请日：1996-12-16
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/265
CPC分类号： H01L27/11521 , H01L27/115
摘要： A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes. Source/drain regions are formed in the second well self-aligned with the stacks as well as spacer dielectric structures formed adjacent to the sidewalls of the stacks. A third doped polysilicon layer patterned into raised bitlines overlies source/drain regions.
摘要翻译：具有掺杂有第一导电类型的半导体衬底上的沟槽的升高位线的非接触式快闪存储器件包括相对导电类型的第一阱，其包括到器件的深导线，以及第一导电类型的第二阱，第一井包括到设备的身体线。深沟槽穿过第二口井进入第一口井。沟槽填充有第一电介质。存在用于闪存器件的栅极电极堆叠，其包括器件上的栅极氧化物层。在栅极氧化物层上形成第一掺杂多晶硅浮栅。在浮栅上形成多晶硅介电层，掺杂多晶硅层形成的控制栅电极覆盖在多晶硅介电层之上。电介质盖覆盖控制栅电极。源极/漏极区域形成在与堆叠体自对准的第二阱以及邻近堆叠的侧壁形成的间隔物电介质结构。图案化为凸起位线的第三掺杂多晶硅层覆盖源极/漏极区域。

6. 发明授权

US06566703B1 High speed flash memory with high coupling ratio 有权
标题翻译：具有高耦合比的高速闪存
公开(公告)号：US06566703B1
公开(公告)日：2003-05-20
申请号：US09665745
申请日：2000-09-20
申请人： Mong-Song Liang , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric layer. A doped silicon semiconductor substrate is covered with variable thickness silicon oxide regions on the surface thereof with junctions between the variable thickness regions. The silicon oxide regions are substantially thicker beneath the center of the floating gate electrode. Source/drain regions formed in the substrate extend beneath the tunnel oxide regions with the junctions aligned with the regions. The floating gate electrodes formed over the silicon oxide regions above the source/drain regions including dielectric sidewalls within the floating gate electrode above the junctions. The variable thickness silicon oxide regions are tunnel oxide regions on either side of a gate oxide region. The floating gate electrode is composed of doped polysilicon and the dielectric sidewalls is reoxidized polysilicon dielectric regions formed within the floating gate electrode above the junctions of the tunnel oxide regions and the gate oxide region.
摘要翻译：闪存器件包括浮栅电极，电极间电介质层和控制栅电极。电极间电介质层形成在浮栅电极的顶部，并且控制栅电极形成在电极间电介质层的顶部。掺杂硅半导体衬底在其表面上被可变厚度的氧化硅区域覆盖，其中可变厚度区域之间具有接合点。氧化硅区域在浮栅电极的中心下方基本上更厚。形成在衬底中的源极/漏极区域在隧道氧化物区域的下方延伸，并且结点与区域对准。形成在源极/漏极区域之上的氧化硅区域上方的浮置栅电极，包括位于结点之上的浮动栅电极内的电介质侧壁。可变厚度的氧化硅区域是栅极氧化物区域两侧的隧道氧化物区域。浮置栅电极由掺杂的多晶硅组成，电介质侧壁是形成在隧道氧化物区域和栅极氧化物区域的结点之上的浮置栅电极内的再氧化的多晶硅介质区域。

7. 发明授权

US06281545B1 Multi-level, split-gate, flash memory cell 有权
标题翻译：多级，分闸，闪存单元
公开(公告)号：US06281545B1
公开(公告)日：2001-08-28
申请号：US09199130
申请日：1998-11-24
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： H01L29788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , G11C2211/5612 , H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

8. 发明授权

US6166410A MONOS flash memory for multi-level logic and method thereof 有权
标题翻译：用于多级逻辑的MONOS闪存及其方法
公开(公告)号：US6166410A
公开(公告)日：2000-12-26
申请号：US166390
申请日：1998-10-05
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： G11C11/56 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/148
CPC分类号： H01L29/7887 , G11C11/5621 , G11C11/5671 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/7923
摘要： The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.
摘要翻译：本发明提供一种制造分闸门MONOS多电平逻辑存储器件的结构和方法。存储器件具有与MONOS晶体管24A串联的多晶硅栅极晶体管20A。该器件具有实现多级存储器存储（例如，4个电压状态）的新颖操作。该方法通过在半导体衬底10的表面上形成隧道氧化物层30开始。衬底在有源区域中具有层叠栅极沟道区域20和MONOS沟道区域24。在堆叠的栅极沟道区域20上形成多晶硅栅极32.在MONOS沟道区24上方，在浮置栅极32和隧道氧化物层上形成具有存储氮化物层的ONO层。形成控制栅电极44 在跨越多晶硅浮栅32和MONOS沟道区24的ONO层41之上。源/漏区50 51形成在衬底中。多晶硅闪光晶体管20A和MONOS闪存晶体管24A组合形成本发明的4电平逻辑存储单元。

9. 发明授权

US5923974A Method of manufacture of memory device with high coupling ratio 失效
标题翻译：具有高耦合比的存储器件的制造方法
公开(公告)号：US5923974A
公开(公告)日：1999-07-13
申请号：US939970
申请日：1997-09-29
申请人： Mong-Song Liang , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/8246
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a semiconductor memory device with a variable thickness gate oxide layer including a tunnel oxide layer and a thicker gate oxide layer includes the following steps. Provide a doped silicon semiconductor substrate coated with a tunnel oxide layer, a first floating gate conductor layer and a dielectric layer. Form a mask with an gate oxide opening through the mask. Etch through the gate oxide opening to form a gate oxide trench through the first polysilicon layer, the dielectric layer and the tunnel oxide layer down to the substrate. Form a gate oxide layer at the base of the gate oxide trench. Deposit a second floating gate conductor layer over the device on the exposed surfaces of the dielectric layer and down into the gate oxide trench including the gate oxide layer. Form a thin interelectrode dielectric layer upon the floating gate conductor layer. Deposit a control gate conductor layer over the device covering the device. Pattern the control gate conductor layer, the thin interelectrode dielectric layer, and the floating gate conductor layer down to the tunnel oxide layer. Form self-aligned source/drain regions in the substrate by a LATI method.
摘要翻译：一种形成具有包括隧道氧化物层和较厚栅极氧化物层的可变厚度栅极氧化物层的半导体存储器件的方法包括以下步骤。提供涂覆有隧道氧化物层，第一浮栅导体层和电介质层的掺杂硅半导体衬底。通过掩模形成具有栅极氧化物开口的掩模。通过栅极氧化物开口蚀刻以形成穿过第一多晶硅层，电介质层和隧道氧化物层的栅极氧化物沟槽，直到衬底。在栅极氧化物沟槽的底部形成栅氧化层。在电介质层的暴露表面上的器件上沉积第二浮栅导体层，并向下沉积到包括栅极氧化物层的栅极氧化物沟槽中。在浮栅导体层上形成薄的电极间电介质层。在覆盖设备的设备上沉积控制栅极导体层。将控制栅极导体层，薄的电极间电介质层和浮动栅极导体层图案化成隧道氧化物层。通过LATI法在衬底中形成自对准的源/漏区。

10. 发明授权

US5834806A Raised-bitline, contactless, trenched, flash memory cell 失效
标题翻译：高架位线，非接触式，沟槽式，闪存单元
公开(公告)号：US5834806A
公开(公告)日：1998-11-10
申请号：US873833
申请日：1997-06-12
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/108 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes. Source/drain regions are formed in the second well self-aligned with the stacks as well as spacer dielectric structures formed adjacent to the sidewalls of the stacks. A third doped polysilicon layer patterned into raised bitlines overlies source/drain regions.
摘要翻译：具有掺杂有第一导电类型的半导体衬底上的沟槽的升高位线的非接触式快闪存储器件包括相对导电类型的第一阱，其包括到器件的深导线，以及第一导电类型的第二阱，第一井包括到设备的身体线。深沟槽穿过第二口井进入第一口井。沟槽填充有第一电介质。存在用于闪存器件的栅极电极堆叠，其包括器件上的栅极氧化物层。在栅极氧化物层上形成第一掺杂多晶硅浮栅。在浮栅上形成多晶硅介电层，掺杂多晶硅层形成的控制栅电极覆盖在多晶硅介电层之上。电介质盖覆盖控制栅电极。源极/漏极区域形成在与堆叠体自对准的第二阱以及邻近堆叠的侧壁形成的间隔物电介质结构。图案化为凸起位线的第三掺杂多晶硅层覆盖源极/漏极区域。

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