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1. 发明申请

US20120168770A1 HEAT DISSIPATION STRUCTURE OF CHIP 审中-公开
标题翻译：芯片散热结构
公开(公告)号：US20120168770A1
公开(公告)日：2012-07-05
申请号：US13391270
申请日：2011-11-18
申请人： Ru Huang , Xin Huang , Tianwei Zhang , Qianqian Huang , Shiqiang Qin
发明人： Ru Huang , Xin Huang , Tianwei Zhang , Qianqian Huang , Shiqiang Qin
IPC分类号： H01L29/20 , H01L29/12
CPC分类号： H01L23/38 , H01L23/3738 , H01L2924/0002 , H01L2924/00
摘要： A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.
摘要翻译：提供了微电子领域的芯片的散热结构。散热结构包括通过氧化隔离在芯片的上表面上形成的P型超晶格层和N型超晶格层。 P型超晶格和N型超晶格被氧化硅隔离。通过接触孔，P型超晶格与在芯片中施加低电位的金属层电连接，并且在P型超晶格上形成与外部电源连接的金属层。通过接触孔，N型超晶格电连接到在芯片中施加高电位电源的金属层，并且在N型超晶格上形成与外部电源连接的金属层。与P型超晶格连接的外部电源的电位低于与N型超晶格连接的外部电源的电位。本发明可以实现芯片的散热，同时通过使用超晶格具有低导热性和声子定位的特性的特征，同时防止环境热量转移到芯片中。

2. 发明授权

US08526242B2 Flash memory and fabrication method and operation method for the same 有权
标题翻译：闪存及其制作方法及操作方法相同
公开(公告)号：US08526242B2
公开(公告)日：2013-09-03
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

3. 发明申请

US20120113726A1 FLASH MEMORY AND FABRICATION METHOD AND OPERATION METHOD FOR THE SAME 有权
标题翻译：闪存及其制造方法和操作方法
公开(公告)号：US20120113726A1
公开(公告)日：2012-05-10
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C16/26 , H01L21/336 , H01L27/115
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

4. 发明授权

US08710557B2 MOS transistor having combined-source structure with low power consumption and method for fabricating the same 有权
标题翻译：具有低功耗的组合源结构的MOS晶体管及其制造方法
公开(公告)号：US08710557B2
公开(公告)日：2014-04-29
申请号：US13501241
申请日：2011-10-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7839
摘要： The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.
摘要翻译：本发明公开了一种具有低功耗的组合源结构的MOS晶体管，其涉及CMOS超大规模集成电路中的场效应晶体管逻辑器件和电路领域。 MOS晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，肖特基源区，高掺杂源极区和高掺杂漏极区。控制栅极的一端延伸到高掺杂源极区域以形成T形，其中控制栅极的延伸区域是延伸栅极，控制栅极的其余区域是主栅极。由延伸栅极覆盖的有源区是沟道区，其材料是衬底材料。在肖特基源区域和延伸栅极下方的通道之间形成肖特基结。根据本发明的组合源结构组合了肖特基势垒和T形门，提高了器件的性能，其制造方法简单。因此，可以获得更高的导通电流，较低的漏电流和更陡的亚阈值斜率，并且本申请可以应用于低功耗领域并具有较高的实用价值。

5. 发明申请

US20120313154A1 MOS Transistor Having Combined-Source Structure With Low Power Consumption and Method for Fabricating the Same 有权
标题翻译：具有低功耗的组合源结构的MOS晶体管及其制造方法
公开(公告)号：US20120313154A1
公开(公告)日：2012-12-13
申请号：US13501241
申请日：2011-10-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7839
摘要： The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.
摘要翻译：本发明公开了一种具有低功耗的组合源结构的MOS晶体管，其涉及CMOS超大规模集成电路中的场效应晶体管逻辑器件和电路领域。 MOS晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，肖特基源区，高掺杂源极区和高掺杂漏极区。控制栅极的一端延伸到高掺杂源极区域以形成T形，其中控制栅极的延伸区域是延伸栅极，控制栅极的其余区域是主栅极。由延伸栅极覆盖的有源区是沟道区，其材料是衬底材料。在肖特基源区域和延伸栅极下方的通道之间形成肖特基结。根据本发明的组合源结构组合了肖特基势垒和T形门，提高了器件的性能，其制造方法简单。因此，可以获得更高的导通电流，较低的漏电流和更陡的亚阈值斜率，并且本申请可以应用于低功耗领域并具有较高的实用价值。

6. 发明授权

US08507959B2 Combined-source MOS transistor with comb-shaped gate, and method for manufacturing the same 有权
标题翻译：具有梳形门的组合源MOS晶体管及其制造方法
公开(公告)号：US08507959B2
公开(公告)日：2013-08-13
申请号：US13318333
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/76 , H01L21/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/66643 , H01L29/7391 , H01L29/7839
摘要： The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.
摘要翻译：本发明公开了一种具有肖特基势垒和梳状栅极结构的组合源MOS晶体管及其制造方法。组合源MOS晶体管包括：控制栅极电极层，栅极电介质层，半导体衬底，高掺杂源极区域和高掺杂漏极区域，其中肖特基源极区域连接到高度远离通道的掺杂源极区域，控制栅极的一端延伸到高掺杂源极区域，延伸栅极区域是梳状形式的延伸栅极，并且原始控制栅极区域是大门; 由延伸栅极覆盖的有源区域也是沟道区域，并且是衬底材料; 通过高掺杂形成的高掺杂源区位于延伸门的每个梳齿的两侧; 并且在肖特基源区域和延伸门下方的沟道所在的位置处形成肖特基结。与现有的MOSFET相比，在本发明中，在相同的工艺条件和相同的有源区域尺寸下可以获得较高的导通电流，较低的漏电流和更陡的亚阈值斜率。

7. 发明申请

US20120223361A1 LOW-POWER CONSUMPTION TUNNELING FIELD-EFFECT TRANSISTOR WITH FINGER-SHAPED GATE STRUCTURE 审中-公开
标题翻译：具有手指形状结构的低功耗消耗隧道场效应晶体管
公开(公告)号：US20120223361A1
公开(公告)日：2012-09-06
申请号：US13378920
申请日：2011-05-19
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/42312 , H01L29/66356
摘要： The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size.
摘要翻译：本发明公开了一种低功耗隧道场效应晶体管（TFET）。根据本发明的TFET包括源极，漏极和控制栅极，其中控制栅极朝向源极延伸以形成指状型控制栅极，其包括扩展栅极区域和原始控制栅极区域，以及主动由扩展栅极区域覆盖的区域也是沟道区域并且由衬底材料制成。本发明采用指形栅极结构，并且TFET的源极区域围绕沟道，使得器件的导通电流得以改善。与传统的平面TFET相比，可以在相同的工艺条件和相同的有源区域尺寸下获得更高的导通电流和更陡的亚阈值斜率。

8. 发明授权

US08877594B2 CMOS device for reducing radiation-induced charge collection and method for fabricating the same 有权
标题翻译：用于减少辐射诱导的电荷收集的CMOS器件及其制造方法
公开(公告)号：US08877594B2
公开(公告)日：2014-11-04
申请号：US13509170
申请日：2011-11-30
申请人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
发明人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
IPC分类号： H01L21/00 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.
摘要翻译：用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。在CMOS器件中，重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。该区域具有与源极区域和漏极区域相反的掺杂类型，并且具有不小于源极区域和漏极区域的掺杂浓度。电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分，并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围，使得可以在电场的力作用下立即收集的电荷减少。

9. 发明授权

US08652929B2 CMOS device for reducing charge sharing effect and fabrication method thereof 有权
标题翻译：用于降低电荷共享效应的CMOS器件及其制造方法
公开(公告)号：US08652929B2
公开(公告)日：2014-02-18
申请号：US13582034
申请日：2012-04-16
申请人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
发明人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
IPC分类号： H01L21/00 , H01L21/02 , H01L21/3063 , H01L21/84
CPC分类号： H01L21/02203 , H01L21/02216 , H01L21/3063 , H01L21/823878 , H01L27/0921
摘要： The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.
摘要翻译：本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。附加隔离区的材料是多孔硅。由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料，因此在多孔硅的表面层上存在大量微孔和悬挂键。这些缺陷可能在多孔硅的禁带的中心形成缺陷状态，缺陷状态可能会捕获载体以引起增加的电阻。随着腐蚀电流密度的增加，孔隙率增加，多孔硅中的缺陷增加。本发明可以通过使用多孔硅捕集载体中的缺陷状态，浅沟槽隔离（STI）区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应，并且该工艺简单，从而可以大大提高集成电路的射电阻性能。

10. 发明申请

US20120181584A1 Resistive Field Effect Transistor Having an Ultra-Steep Subthreshold Slope and Method for Fabricating the Same 审中-公开
标题翻译：具有超陡亚阈值斜率的电阻场效应晶体管及其制造方法
公开(公告)号：US20120181584A1
公开(公告)日：2012-07-19
申请号：US13318329
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/435
摘要： The invention discloses a resistive field effect transistor (ReFET) having an ultra-steep subthreshold slope, which relates to a field of field-effect-transistor logic device and circuit in CMOS ultra-large-scale-integrated circuit (ULSI). The resistive field effect transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a doped source region and a doped drain region, wherein the control gate is configured to adopt a stacked gate structure in which a bottom layer or a bottom electrode layer, a middle layer or a resistive material layer, and a top layer or a top electrode layer are sequentially formed. Compared with the existing methods for breaking the conventional subthreshold slope limititation, the device of the invention has a larger on-current, a lower operation voltage, and a better subthreshold feature.
摘要翻译：本发明公开了一种具有超陡亚阈值斜率的电阻场效应晶体管（ReFET），其涉及CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件和电路的场。电阻场效应晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，掺杂源极区域和掺杂漏极区域，其中控制栅极被配置为采用堆叠栅极结构，其中底层或顺序地形成底部电极层，中间层或电阻材料层，顶层或顶部电极层。与现有的破坏常规阈值斜率限制的方法相比，本发明的器件具有较大的导通电流，较低的工作电压和更好的亚阈值特性。

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