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1. 发明授权

US07286595B2 Apparatus using a lengthened equalization target filter with a matched filter metric in a viterbi detector 失效
标题翻译：在维特比检测器中使用具有匹配滤波器度量的延长均衡目标滤波器的装置
公开(公告)号：US07286595B2
公开(公告)日：2007-10-23
申请号：US10683645
申请日：2003-10-10
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos Eleftheriou , Richard L. Galbraith , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos Eleftheriou , Richard L. Galbraith , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03K9/00
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10055 , G11B20/10296
摘要： An apparatus that uses a lengthened equalization target filter with a matched filter metric in a Viterbi detector is disclosed. The equalization target includes a base partial response component, i.e., (1−D2), a fractional coefficient polynomial component to whiten the noise, i.e., (1+p1D+p2D2), and a time-reversed replica of the noise-whitening component. Thus, the time-reversed replica of the noise-whitening component comes from what was formerly a matched filter component.
摘要翻译：公开了一种在维特比检测器中使用具有匹配滤波器度量的延长均衡目标滤波器的装置。均衡目标包括基本部分响应分量，即（1-D 2），用于使噪声变白的分数系数多项式分量，即（1 + p < D + p 2 D 2 O 2）和噪声增白部件的时间反转复制品。因此，噪声增白部件的时间反转复制品来自以前的匹配滤波器部件。

2. 发明授权

US07173784B2 Apparatus for providing data dependent detection in a data read channel 失效
标题翻译：用于在数据读取通道中提供数据相关检测的装置
公开(公告)号：US07173784B2
公开(公告)日：2007-02-06
申请号：US10683646
申请日：2003-10-10
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos Eleftheriou , Richard L. Galbraith , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos Eleftheriou , Richard L. Galbraith , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： G11B5/09 , H03M13/03 , H03D1/00
CPC分类号： G11B20/10296 , G11B20/10009 , G11B20/24
摘要： An apparatus for providing data dependent detection in a data read channel is disclosed. Parameters in a read channel are dynamically adjusted according to data dependent noise. For example, a comparison in an add-compare-select (ACS) unit of a Viterbi decoder may be adjusted or offset terms in error event filters may be biased to choose a Viterbi sequence with more transitions or to compensate for polarity dependent noise.
摘要翻译：公开了一种用于在数据读取通道中提供数据相关检测的装置。读通道中的参数根据数据相关噪声进行动态调整。例如，可以调整维特比解码器的加法比较选择（ACS）单元中的比较，或者错误事件滤波器中的偏移项可能被偏置以选择具有更多跃迁的维特比序列或补偿极性相关噪声。

3. 发明授权

US07395482B2 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US07395482B2
公开(公告)日：2008-07-01
申请号：US10739966
申请日：2003-12-18
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，调制解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的预编码应用于调制编码比特流。然而，该预编码仅应用于位流的选定部分。还可以存在一个置换步骤，其中在由预编码器施加预编码之前，该位序列在调制编码器之后被置换。解码器子系统以相反的方式运行。

4. 发明授权

US07193802B2 Apparatus for providing dynamic equalizer optimization 失效
标题翻译：用于提供动态均衡器优化的装置
公开(公告)号：US07193802B2
公开(公告)日：2007-03-20
申请号：US10809230
申请日：2004-03-25
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning , Michael J. Ross , David J. Stanek
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning , Michael J. Ross , David J. Stanek
IPC分类号： G11B5/09 , G11B5/035 , H03K5/139
CPC分类号： G11B5/035
摘要： An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.
摘要翻译：公开了一种用于提供动态均衡器优化的装置。本发明通过提供均衡器系数更新来解决上述问题，所述均衡器系数更新收敛于与直接方法相同的解决方案，而不必首先将已知模式写入盘或需要任何已经写入盘中的数据的任何知识。自适应余弦函数可用于仅修改DFIR抽头集，仅修改余弦均衡器的j和k参数，或者修改DFIR滤波器的抽头集合和余弦均衡器的j和k参数。可以使用诸如LMS算法的另一种算法来修改未被余弦算法修改的参数。

5. 发明授权

US08276038B2 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US08276038B2
公开(公告)日：2012-09-25
申请号：US11833274
申请日：2007-08-03
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03M7/46 , H03M13/03 , G11B20/18
CPC分类号： H03M5/145 , G11B20/1833 , G11B2020/1836 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/6343
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，信道解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的前面应用于调制编码比特流。然而，上述内容仅适用于位流的选定部分。还可以存在一个置换步骤，其中比特序列在调制编码器之前被预编码器施加之前被置换。解码器子系统以相反的方式运行。

6. 发明授权

US07694205B2 Method and apparatus for providing a read channel having combined parity and non-parity post processing 有权
标题翻译：用于提供具有组合奇偶校验和非奇偶校验后处理的读通道的方法和装置
公开(公告)号：US07694205B2
公开(公告)日：2010-04-06
申请号：US11067851
申请日：2005-02-28
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/45 , G11B20/10009 , G11B20/10055 , G11B20/1833 , G11B2020/1863 , H03M13/098 , H03M13/6343
摘要： A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.
摘要翻译：公开了一种用于提供具有组合奇偶校验和非奇偶校验后处理的读通道的方法和装置。后处理器组合奇偶校验和非奇偶校验后处理以进行奇偶校验和非奇偶校正，从而校正不能被奇偶校验检测到的错误事件。只有当它们的可能性高于设定的阈值时，才能保持非奇偶校验可检测误差事件。

7. 发明授权

US06812867B2 Data coding for data storage systems 失效
标题翻译：数据存储系统的数据编码
公开(公告)号：US06812867B2
公开(公告)日：2004-11-02
申请号：US10455696
申请日：2003-06-05
申请人： Roy D Cideciyan , Ajay Dholakia , Evangelos S Eleftheriou , Richard L Galbraith , Thomas Mittelholzer , Travis R Oenning , David J Stanek
发明人： Roy D Cideciyan , Ajay Dholakia , Evangelos S Eleftheriou , Richard L Galbraith , Thomas Mittelholzer , Travis R Oenning , David J Stanek
IPC分类号： H03M700
CPC分类号： H03M7/46 , G11B20/1426 , G11B2020/1446 , H03M5/145
摘要： Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.
摘要翻译：描述了一种具有有限状态机的调制编码器，用于将输入比特转换成输出比特，其中交替输出比特的数量被限制为j + 1，其中j是输出比特中的预定义的最大转移数，类似的输出位被限制为k + 1，其中k是输出位中的非转换的预定最大数量。调制编码器可以用于将输入比特流转换成输出比特流的编码装置。这种装置可以包括用于将输入比特流分成第一组比特和第二组比特的分区逻辑。多个上述调制编码器可以连接到用于将第一组位转换为编码输出位的分割逻辑。组合逻辑可以连接到或每个调制编码器和用于组合编码的输出位和第二组位的分区逻辑以产生输出比特流。还描述了对位调制解码器和解码装置。

8. 发明申请

US20090089645A1 DATA STORAGE SYSTEMS 审中-公开
标题翻译：数据存储系统
公开(公告)号：US20090089645A1
公开(公告)日：2009-04-02
申请号：US12058151
申请日：2008-03-28
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： Method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream in dependence on the output bit stream and the data block. An error correction decoder connected to the post processor generates a second error corrected bit stream in dependence on the first error corrected bit stream and also generates a checksum in dependence of the second error corrected bit stream. A feedback path supplies from the error correction decoder to the post processor pinning data indicative of locations of correct bits in the second error corrected bit stream in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave. The post processor regenerates the first error corrected bit stream in dependence on the pinning data received from the error correction decoder.
摘要翻译：用于在数据存储系统中解码数据的方法和装置。在操作中，检测器根据从数据存储系统的存储子系统接收的数据块产生输出位流。连接到检测器的后处理器根据输出比特流和数据块生成第一纠错比特流。连接到后处理器的纠错解码器根据第一纠错比特流产生第二纠错比特流，并且还根据第二纠错比特流产生校验和。在校验和指示第二纠错比特流中的错误并且校正的第二错误的情况下，反馈路径从错误校正解码器向后处理器提供钉扎指示第二纠错比特流中的正确比特的位置的数据位流包括至少一个正确的交错。后处理器根据从纠错解码器接收到的钉扎数据重新生成第一纠错比特流。

9. 发明授权

US07574646B2 Data storage systems 失效
标题翻译：数据存储系统
公开(公告)号：US07574646B2
公开(公告)日：2009-08-11
申请号：US11286582
申请日：2005-11-25
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： A method for decoding data in a data storage system includes generating an output bit stream; generating a first error corrected bit stream in dependence on the output bit stream; generating a second error corrected bit stream in dependence on the first error corrected bit stream; generating a checksum in dependence of the second error corrected bit stream; and, in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave: supplying data indicative of locations of correct bits in the second error corrected bit stream; and, regenerating the first error corrected bit stream in dependence on the pinning data.
摘要翻译：一种用于在数据存储系统中解码数据的方法包括：生成输出比特流; 根据输出比特流产生第一纠错比特流; 根据第一纠错比特流产生第二纠错比特流; 根据第二纠错比特流产生校验和; 并且在所述校验和指示所述第二纠错比特流中的错误并且所述第二纠错比特流包括至少一个正确交错的情况下：提供指示所述第二纠错比特流中的正确比特的位置的数据; 以及根据钉扎数据再生第一纠错比特流。

10. 发明申请

US20050138518A1 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US20050138518A1
公开(公告)日：2005-06-23
申请号：US10739966
申请日：2003-12-18
申请人： Roy Cideciyan , Ajay Dholakia , Evangelos Eleftheriou , Richard Galbraith , Weldon Hanson , Thomas Mittelholzer , Travis Oenning
发明人： Roy Cideciyan , Ajay Dholakia , Evangelos Eleftheriou , Richard Galbraith , Weldon Hanson , Thomas Mittelholzer , Travis Oenning
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03M13/00
CPC分类号： G11B20/1833
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，信道解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的预编码应用于调制编码比特流。然而，该预编码仅应用于位流的选定部分。还可以存在一个置换步骤，其中在由预编码器施加预编码之前，该位序列在调制编码器之后被置换。解码器子系统以相反的方式运行。

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