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1. 发明授权

US5612547A Silicon carbide static induction transistor 失效
标题翻译：碳化硅静电感应晶体管
公开(公告)号：US5612547A
公开(公告)日：1997-03-18
申请号：US462405
申请日：1995-06-05
申请人： Rowland C. Clarke , Richard R. Siergiej , Saptharishi Sriram
发明人： Rowland C. Clarke , Richard R. Siergiej , Saptharishi Sriram
IPC分类号： H01L29/24 , H01L29/772 , H01L29/808 , H01L29/812 , H01L31/0312 , H01L27/095 , H01L29/80 , H01L31/112
CPC分类号： H01L29/1608 , H01L29/7722 , H01L29/8083 , H01L29/8122
摘要： A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.
摘要翻译：尽管可以使用任何碳化硅多型体，但由碳化硅制成的静电感应晶体管，优选为6H型。优选的静态感应晶体管是凹入的肖特基势垒栅型。因此，提供了碳化硅衬底。然后，在基板上设置碳化硅漂移层，其中漂移层具有远离衬底延伸的两个间隔开的突起或指状物。漂移层的每个突起具有设置在其上的碳化硅源区域。然后沿两个突起之间的漂移层提供栅极材料。在栅极材料上提供导电栅极触点，并且在每个源极区域上提供导电源极触点。沿着衬底提供导电漏极接触。考虑静态感应晶体管的其他栅极类型。例如，可以采用平面肖特基势垒栅极。此外，可以使用凹入或平面的MOS栅极，如PN结栅极。

2. 发明授权

US5807773A Self-aligned gate fabrication process for silicon carbide static induction transistors 失效
标题翻译：碳化硅静电感应晶体管的自对准栅极制造工艺
公开(公告)号：US5807773A
公开(公告)日：1998-09-15
申请号：US688587
申请日：1996-07-30
申请人： Li-Shu Chen , Rowland C. Clarke , Richard R. Siergiej
发明人： Li-Shu Chen , Rowland C. Clarke , Richard R. Siergiej
IPC分类号： H01L21/04 , H01L21/337
CPC分类号： H01L29/66068 , Y10S438/931
摘要： A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.
摘要翻译：一种对准碳化硅静电感应晶体管的栅极和源极的方法，包括以下步骤：在所述晶体管上沉积氧化物层，从所述氧化物层形成氧化物间隔物，其中所述氧化物间隔物邻近所述源，在所述氧化物层上沉积金属层去除氧化物间隔物，使得所得到的栅极与源极准确对准。

3. 发明授权

US5945701A Static induction transistor 失效
标题翻译：静电感应晶体管
公开(公告)号：US5945701A
公开(公告)日：1999-08-31
申请号：US995080
申请日：1997-12-19
申请人： Richard R. Siergiej , Anant K. Agarwal , Rowland C. Clarke , Charles D. Brandt
发明人： Richard R. Siergiej , Anant K. Agarwal , Rowland C. Clarke , Charles D. Brandt
IPC分类号： H01L29/80 , H01L29/12 , H01L29/772 , H01L29/78 , H01L29/808 , H01L29/812
CPC分类号： H01L29/7722
摘要： A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.
摘要翻译：具有源极，漏极和栅极区域的静态感应晶体管。沟道区域被定义在相邻栅极之间，并且从沟道区域的端部到漏极限定漂移区域。通道和漂移区具有预定的掺杂浓度，其中沟道区的掺杂浓度大于漂移区的掺杂浓度。

4. 发明授权

US5903020A Silicon carbide static induction transistor structure 失效
标题翻译：碳化硅静电感应晶体管结构
公开(公告)号：US5903020A
公开(公告)日：1999-05-11
申请号：US877847
申请日：1997-06-18
申请人： Richard R. Siergiej , Anant K. Agarwal , Rowland C. Clarke , Charles D. Brandt
发明人： Richard R. Siergiej , Anant K. Agarwal , Rowland C. Clarke , Charles D. Brandt
IPC分类号： H01L21/04 , H01L29/06 , H01L29/24 , H01L29/772 , H01L29/80
CPC分类号： H01L29/7722 , H01L29/66068 , H01L29/0619 , H01L29/0696 , H01L29/1608 , H01L29/32
摘要： A static induction transistor having a silicon carbide substrate upon which is deposited a silicon carbide layer arrangement. The layer arrangement has a plurality of spaced gate regions for controlling current flow from a source region to a drain region vertically spaced from the source region by a drift layer. The pitch distance p between gate regions is 1 to 5 microns and the drift layer thickness d is also 1 to 5 microns.In one embodiment the source regions are positioned alternatively with the gate regions and are formed in a top layer of high doping concentration. In another embodiment the gate regions are ion implanted in the layer arrangement.In another embodiment the structure includes a dual oxide layer covering gate and source or drain regions, and in yet another embodiment contacts for the drain, source and gate regions are located on the same side of the substrate member.
摘要翻译：一种具有碳化硅衬底的静电感应晶体管，沉积碳化硅层布置。层布置具有多个间隔开的栅极区域，用于控制从源极区域到通过漂移层与源极区域垂直间隔开的漏极区域的电流。栅区之间的间距距离p为1至5微米，漂移层厚度d也为1至5微米。在一个实施例中，源极区域与栅极区域交替定位并且形成在高掺杂浓度的顶层中。在另一个实施例中，栅极区域被离子注入层布置。在另一个实施例中，该结构包括覆盖栅极和源极或漏极区域的双重氧化物层，并且在又一实施例中，用于漏极，源极和栅极区域的触点位于衬底构件的相同侧上。

5. 发明授权

US5705830A Static induction transistors 失效
标题翻译：静电感应晶体管
公开(公告)号：US5705830A
公开(公告)日：1998-01-06
申请号：US708447
申请日：1996-09-05
申请人： Richard R. Siergiej , Anant K. Agarwal , Rowland C. Clarke , Charles D. Brandt
发明人： Richard R. Siergiej , Anant K. Agarwal , Rowland C. Clarke , Charles D. Brandt
IPC分类号： H01L21/04 , H01L29/772 , H01L31/0312
CPC分类号： H01L29/66068 , H01L29/7722
摘要： A static induction transistor includes a substrate and a drift layer with different doping levels. At least two mesas are formed on the drift layer and a heavily doped region is positioned on a top surface of each of the mesas. A gate contact extends along a bottom of a recess between the mesas and along a side of each of the mesas forming the recess. The gate contact also extends along a portion of the top surface of each of the mesas. In one embodiment of the invention, a notch is formed in the top surface of the mesas between the gate contact and the heavily doped region.
摘要翻译：静电感应晶体管包括衬底和具有不同掺杂水平的漂移层。在漂移层上形成至少两个台面，并且重掺杂区域位于每个台面的顶表面上。栅极接触沿着台面之间的凹部的底部并沿着形成凹部的每个台座的一侧延伸。栅极接触还沿着每个台面的顶表面的一部分延伸。在本发明的一个实施例中，在栅极接触和重掺杂区域之间的台面的顶表面中形成有凹口。

6. 发明授权

US5925895A Silicon carbide power MESFET with surface effect supressive layer 失效
标题翻译：碳化硅功率MESFET具有表面效应抑制层
公开(公告)号：US5925895A
公开(公告)日：1999-07-20
申请号：US812227
申请日：1997-03-06
申请人： Saptharishi Sriram , Rowland C. Clarke
发明人： Saptharishi Sriram , Rowland C. Clarke
IPC分类号： H01L21/04 , H01L29/24 , H01L29/812 , H01L31/0312 , H01L29/12
CPC分类号： H01L29/1608 , H01L21/045 , H01L29/66068 , H01L29/8128
摘要： A silicon carbide metal semiconductor field effect transitor fabricated on silicon carbide substrate with a layer which suppresses surface effects, and method for producing same. The surface-effect-suppressive layer may be formed on exposed portions of the transistor channel and at least a portion of each contact degenerate region. The surface-effect-suppressive layer may be made of undoped silicon carbide or of an insulator, such as silicon dioxide or silicon nitride. If the surface-effect-suppressive layer is made of silicon dioxide, it is preferred that the layer be fabricated of a combination of thermally-grown and chemical vapor deposition deposited silicon dioxide.
摘要翻译：在具有抑制表面效应的层的碳化硅衬底上制造的碳化硅金属半导体场效应晶体管及其制造方法。表面效应抑制层可以形成在晶体管沟道的暴露部分和每个接触退化区域的至少一部分上。表面效应抑制层可以由未掺杂的碳化硅或诸如二氧化硅或氮化硅的绝缘体制成。如果表面效应抑制层由二氧化硅制成，则优选由热生长和化学气相沉积沉积的二氧化硅的组合制成该层。

7. 发明授权

US5501173A Method for epitaxially growing .alpha.-silicon carbide on a-axis .alpha.-silicon carbide substrates 失效
标题翻译：在a轴碳化硅基体上外延生长α-碳化硅的方法
公开(公告)号：US5501173A
公开(公告)日：1996-03-26
申请号：US138564
申请日：1993-10-18
申请人： Albert A. Burk, Jr. , Donovan L. Barrett , Hudson M. Hobgood , Rowland C. Clarke , Graeme W. Eldridge , Charles D. Brandt
发明人： Albert A. Burk, Jr. , Donovan L. Barrett , Hudson M. Hobgood , Rowland C. Clarke , Graeme W. Eldridge , Charles D. Brandt
IPC分类号： C30B25/02 , C30B25/20 , H01L21/205
CPC分类号： H01L21/02378 , C30B25/02 , C30B29/36 , H01L21/02529 , H01L21/02576 , H01L21/0262 , Y10S148/148 , Y10S438/931
摘要： A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.
摘要翻译：提供了在a轴基板上外延生长a轴α-SiC的方法。通过在晶体中形成一对平行切口，从SiC晶体形成截面。这些切口中的每一个平行于晶体的c轴。由晶体形成的部分具有与晶体的c轴平行的相对的a面表面。具有烃和硅烷的气体混合物通过该部分的一个面表面。烃和硅烷在该表面上反应形成SiC的外延层。优选地，SiC在大约1450℃的温度下生长。

8. 发明授权

US5198695A Semiconductor wafer with circuits bonded to a substrate 失效
标题翻译：具有与衬底结合的电路的半导体晶片
公开(公告)号：US5198695A
公开(公告)日：1993-03-30
申请号：US624783
申请日：1990-12-10
申请人： Maurice H. Hanes , Rowland C. Clarke , Michael C. Driver
发明人： Maurice H. Hanes , Rowland C. Clarke , Michael C. Driver
IPC分类号： H01L23/373 , H01L23/498
CPC分类号： H01L23/49866 , H01L23/3731 , H01L23/49827 , H01L2924/0002
摘要： A bonded structure is described consisting of a semiconductor wafer, preferably gallium arsenide, soldered to a substrate material. A method for forming the structure is also described. The structure provides mechanical support and thermal conductivity for the wafer, as well as a multitude of connections through the substrate material at predetermined locations on the wafer. The substrate material and the soldering process are selected to minimize the resulting stresses in the wafer. A pattern of pads consisting of a refractory metal covered by a solder material is formed on the substrate to maintain space for excess solder in order to avoid the shorting of the individual connections on the wafer, and to control the size and location of voids in the solder upon solidification.
摘要翻译：描述了焊接到基底材料的半导体晶片，优选砷化镓的结合结构。还描述了用于形成结构的方法。该结构为晶片提供机械支撑和导热性，以及在晶片上的预定位置处通过衬底材料的多个连接。选择衬底材料和焊接工艺以最小化晶片中产生的应力。在衬底上形成由焊料材料覆盖的难熔金属组成的衬垫图案，以保持多余焊料的空间，以避免晶片上的各个连接的短路，并且控制空隙的尺寸和位置焊后固化。

9. 发明授权

US4583107A Castellated gate field effect transistor 失效
标题翻译： Castellated栅场效应晶体管
公开(公告)号：US4583107A
公开(公告)日：1986-04-15
申请号：US523819
申请日：1983-08-15
申请人： Rowland C. Clarke
发明人： Rowland C. Clarke
IPC分类号： H01L29/423 , H01L29/812 , H01L29/80 , H01L29/06 , H01L29/36 , H01L29/48
CPC分类号： H01L29/812 , H01L29/42316
摘要： A field effect transistor is described incorporating a semiconductor layer over a layer or substrate of semi-insulating semiconductor material and a gate electrode which periodically passes through the semiconductor layer to the substrate to form a plurality of conducting bars in the semiconductor layer for transistor current and which at pinch-off confines the current interior of each conducting bar. The invention overcomes the problem of leakage current at pinch-off, thus improving the efficiency of the field effect transistor as a power amplifier.
摘要翻译：描述了一种场效应晶体管，其在半绝缘半导体材料的层或衬底上的半导体层和周期性地通过半导体层到衬底以在晶体管电流的半导体层中形成多个导电棒的栅电极，以及这在夹断时限制了每个导电棒的当前内部。本发明克服了夹断漏电流的问题，提高了作为功率放大器的场效应晶体管的效率。

10. 发明授权

US07560322B2 Method of making a semiconductor structure for high power semiconductor devices 有权
标题翻译：制造大功率半导体器件的半导体结构的方法
公开(公告)号：US07560322B2
公开(公告)日：2009-07-14
申请号：US11248195
申请日：2005-10-13
申请人： Rowland C. Clarke , Robert S. Howell , Michael E. Aumer
发明人： Rowland C. Clarke , Robert S. Howell , Michael E. Aumer
IPC分类号： H01L21/338 , H01L21/30
CPC分类号： H01L21/76256 , H01L21/76254 , H01L21/8213 , H01L21/8258 , H01L21/84 , H01L27/0605 , H01L29/2003 , H01L29/6606 , H01L29/66068 , H01L29/735 , H01L29/7787
摘要： A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO2 of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.
摘要翻译：用于大功率半导体器件的衬底布置包括在SiC晶片的表面上沉积有Si层的SiC晶片。具有Si的第一层，SiO 2的中间层和Si的第三层的SOI结构具有与沉积在SiC晶片上的Si结合的第三层Si，形成整体结构。除去SOI的第一层和SiO 2的中间层，留下可以制造各种半导体器件的纯的第三层Si。可以在衬底布置的一部分上去除第三层Si和沉积的Si层，使得可以在SiC晶片上制造一个或多个半导体器件，而其他半导体器件可以容纳在纯的第三层Si上。

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