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1. 发明授权

US07171543B1 Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor 有权
标题翻译：通过将应用程序限制在64位处理器中的32位地址空间子集来执行32位应用程序的方法和装置
公开(公告)号：US07171543B1
公开(公告)日：2007-01-30
申请号：US09536452
申请日：2000-03-28
申请人： Ronny Ronen , Alexander Peleg
发明人： Ronny Ronen , Alexander Peleg
IPC分类号： G06F9/34
CPC分类号： G06F9/3017 , G06F9/342
摘要： Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.
摘要翻译：执行端口到第二位大小环境的第一位大小的应用的指令的装置和方法，包括将应用限制到第一位大小地址空间子集的方法和装置。根据本发明的实施例包括将应用限制到地址空间子集的方法，所述方法包括确定所述应用被限制在第一位大小地址子集中，所述应用包括指令; 生成第二位大小的地址参考作为指令的执行的一部分; 将所生成的地址引用从第二位大小截断到第一位大小; 以及至少部分地基于地址格式控制标志将截断的所生成的地址引用从第一位大小扩展到第二位大小。

2. 发明授权

US06675376B2 System and method for fusing instructions 有权
标题翻译：用于定影指令的系统和方法
公开(公告)号：US06675376B2
公开(公告)日：2004-01-06
申请号：US09752233
申请日：2000-12-29
申请人： Ronny Ronen , Alexander Peleg , Nathaniel Hoffman
发明人： Ronny Ronen , Alexander Peleg , Nathaniel Hoffman
IPC分类号： G06F945
CPC分类号： G06F9/3001 , G06F9/30123 , G06F9/3017 , G06F9/3853 , G06F9/3893
摘要： A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed. In one embodiment, the execution unit has two arithmetic logic units (“ALUs”), each of the ALUs performs one of the two operations of the fused instruction. The result of the first ALU is input into the second ALU to produce the desired result.
摘要翻译：描述用于产生融合指令的系统和方法。在一个实施例中，作为简单指令（例如，仅执行一个操作）并且是依赖的第一指令和第二指令被融合在一起以创建融合指令。融合指令具有表示由第一指令执行的操作和由第二指令执行的操作的操作码。融合指令有三个源操作数和一个目标操作数。三个源操作数中的两个是第一个指令的两个源操作数，第三个源操作数是不是第一个指令的目标操作数的第二个指令的源操作数。融合指令的目标操作数是第二条指令的目标操作数。还公开了可以在一个时钟周期执行融合指令的执行单元。在一个实施例中，执行单元具有两个算术逻辑单元（“ALU”），每个ALU执行融合指令的两个操作之一。将第一ALU的结果输入到第二ALU中以产生期望的结果。

3. 发明授权

US08874882B1 Compiler-directed sign/zero extension of a first bit size result to overwrite incorrect data before subsequent processing involving the result within an architecture supporting larger second bit size values 有权
标题翻译：第一位大小结果的编译器引导符号/零扩展在覆盖支持更大的第二位大小值的体系结构内的结果的后续处理之前覆盖不正确的数据
公开(公告)号：US08874882B1
公开(公告)日：2014-10-28
申请号：US09539436
申请日：2000-03-30
申请人： Ronny Ronen , Alexander Peleg
发明人： Ronny Ronen , Alexander Peleg
IPC分类号： G06F9/318 , G06F9/302 , G06F9/45 , G06F9/30
CPC分类号： G06F9/30181 , G06F8/41 , G06F8/447 , G06F9/3001 , G06F9/30014 , G06F9/30112 , G06F9/30192
摘要： Apparatus and methods to add an extended first bit size data item of a first source operand specified by an instruction to a second source operand specified by the instruction. The first source operand and the second source operand are a second bit size, the second bit size being greater than the first bit size. The result of adding the extended data item of the first source operand to the second source operand can be stored.
摘要翻译：将由指令指定的第一源操作数的扩展的第一位大小数据项添加到由指令指定的第二源操作数的装置和方法。第一源操作数和第二源操作数是第二位大小，第二位大小大于第一位大小。可以存储将第一源操作数的扩展数据项添加到第二源操作数的结果。

4. 发明授权

US07458069B2 System and method for fusing instructions 有权
标题翻译：用于定影指令的系统和方法
公开(公告)号：US07458069B2
公开(公告)日：2008-11-25
申请号：US10752875
申请日：2004-01-06
申请人： Ronny Ronen , Alexander Peleg , Nathaniel Hoffman
发明人： Ronny Ronen , Alexander Peleg , Nathaniel Hoffman
IPC分类号： G06F9/45
CPC分类号： G06F9/3001 , G06F9/30123 , G06F9/3017 , G06F9/3853 , G06F9/3893
摘要： A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed. In one embodiment, the execution unit has two arithmetic logic units (“ALUs”), each of the ALUs performs one of the two operations of the fused instruction. The result of the first ALU is input into the second ALU to produce the desired result.
摘要翻译：描述用于产生融合指令的系统和方法。在一个实施例中，作为简单指令（例如，仅执行一个操作）并且是依赖的第一指令和第二指令被融合在一起以创建融合指令。融合指令具有表示由第一指令执行的操作和由第二指令执行的操作的操作码。融合指令有三个源操作数和一个目标操作数。三个源操作数中的两个是第一个指令的两个源操作数，第三个源操作数是不是第一个指令的目标操作数的第二个指令的源操作数。融合指令的目标操作数是第二条指令的目标操作数。还公开了可以在一个时钟周期执行融合指令的执行单元。在一个实施例中，执行单元具有两个算术逻辑单元（“ALU”），每个ALU执行融合指令的两个操作之一。将第一ALU的结果输入到第二ALU中以产生期望的结果。

5. 发明申请

US20130124834A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130124834A1
公开(公告)日：2013-05-16
申请号：US13730848
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

6. 发明申请

US20130117538A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130117538A1
公开(公告)日：2013-05-09
申请号：US13730839
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

7. 发明授权

US08396915B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08396915B2
公开(公告)日：2013-03-12
申请号：US13603370
申请日：2012-09-04
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

8. 发明申请

US20120198210A1 Microprocessor Having Novel Operations 失效
标题翻译：具有新颖操作的微处理器
公开(公告)号：US20120198210A1
公开(公告)日：2012-08-02
申请号：US13444090
申请日：2012-04-11
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
摘要翻译：处理器处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。解码器具有控制信号输入。控制信号输入用于接收第一控制信号和第二控制信号。第一控制信号用于指示包装操作。第二控制信号用于指示解封装操作。功能单元耦合到解码器和寄存器。功能单元用于使用第一打包数据执行包操作和拆包操作。处理器还支持移动操作。

9. 发明授权

US07966482B2 Interleaving saturated lower half of data elements from two source registers of packed data 失效
标题翻译：从包装数据的两个源寄存器中交织饱和的下半部分数据元素
公开(公告)号：US07966482B2
公开(公告)日：2011-06-21
申请号：US11451906
申请日：2006-06-12
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/315
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。从第一源寄存器接收第一打包数据元素和第二打包数据元素。从第二源寄存器接收第三压缩数据元素和第四打包数据元素。所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分从第三个打包的数据元素。

10. 发明申请

US20050114628A1 Method and apparatus to support an expanded register set 有权
标题翻译：支持扩展寄存器集的方法和装置
公开(公告)号：US20050114628A1
公开(公告)日：2005-05-26
申请号：US10625240
申请日：2003-07-22
申请人： Opher Kahn , Alexander Peleg , Bob Valentine
发明人： Opher Kahn , Alexander Peleg , Bob Valentine
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30134 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： Processors and methods having an expanded logical register set. In one embodiment, a processor includes Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set can include more than eight logical registers of a first type.
摘要翻译：具有扩展逻辑寄存器集的处理器和方法。在一个实施例中，处理器包括Intel架构32（IA-32）指令集解码逻辑和扩展的逻辑寄存器组。扩展逻辑寄存器集可以包括多于八个第一类型的逻辑寄存器。

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