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1. 发明授权

US07848473B2 Phase interpolator having a phase jump 有权
标题翻译：相位内插器具有相位跳变
公开(公告)号：US07848473B2
公开(公告)日：2010-12-07
申请号：US11020021
申请日：2004-12-22
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H04L7/04
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0337
摘要： A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.
摘要翻译：公开了一种基于漫游抽头内插器来产生相位控制数据的方法和装置。本发明认识到，漫游抽头内插器在每个内插区域的边界处具有固有的非线性和不连续性。公开了一种漫游抽头内插器，其在时间上偏移插值曲线，以避免插值曲线中的不需要的伪影。漫游抽头内插器通常包括多个延迟元件，其延迟第一信号以产生每个具有相关联的相位的多个内插区域; 多路复用器，用于选择一个或多个插值区域; 以及内插器，用于处理所选择的一个或多个内插区域以产生第二信号。此外，根据本发明，漫游抽头内插器包括延迟单元，其选择性地延迟第一信号和第二信号中的一个或多个以产生内插信号，该内插信号选择性地具有第一相位或第二相位。

2. 发明授权

US07928789B2 Methods and apparatus for improved phase switching and linearity in an analog phase interpolator 有权
标题翻译：用于改善模拟相位内插器中的相位切换和线性度的方法和装置
公开(公告)号：US07928789B2
公开(公告)日：2011-04-19
申请号：US12344047
申请日：2008-12-24
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K11/16
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位内插器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

3. 发明授权

US07495494B2 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
标题翻译：用于电压控制延迟回路的平行修整方法和装置
公开(公告)号：US07495494B2
公开(公告)日：2009-02-24
申请号：US11141703
申请日：2005-05-31
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
摘要翻译：提供了一种用于电压控制延迟环路的并行修整方法和装置。电压控制延迟环中的多个延迟单元被修整。每个延迟单元包括延迟元件和锁存缓冲器。参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

4. 发明授权

US07205811B2 Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias 有权
标题翻译：使用可调偏置在相位内插器中保持时钟边缘期望斜率的方法和装置
公开(公告)号：US07205811B2
公开(公告)日：2007-04-17
申请号：US11095772
申请日：2005-03-31
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03K6/04
摘要： Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.
摘要翻译：提供的方法和装置用于使用可调偏置来保持相位插值器中的时钟边缘的期望斜率。所公开的相位插值器包括至少一个延迟元件，以产生每个具有相关联的相关联的至少两个插值信号和与至少两个内插信号中的每一个相关联的可变斜率单元，其中每个可变斜率单元的斜率被控制通过偏置信号，并且基于插值信号的数据速率而变化。改变斜率以保持与内插信号相关联的时钟边缘的期望斜率。斜率可以维持在例如在连续时钟边缘之间的延迟的近似值和连续时钟边缘之间的延迟值的两倍之间。

5. 发明授权

US07190198B2 Voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟回路
公开(公告)号：US07190198B2
公开(公告)日：2007-03-13
申请号：US10999889
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03L7/06
CPC分类号： G06F1/04
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。中央插值器提供精细的相位控制。此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

6. 发明授权

US07173459B2 Trimming method and apparatus for voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟环微调方法和装置
公开(公告)号：US07173459B2
公开(公告)日：2007-02-06
申请号：US11020022
申请日：2004-12-22
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0818
摘要： Methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. The trimming method may be repeated for each delay element in a voltage controlled delay loop.
摘要翻译：提供了用于在电压控制的延迟环中修整期望的延迟元件的方法和装置。所公开的修剪过程包括获得参考时钟的第一相位信号的步骤; 将第一相位信号沿着第一路径施加到期望的延迟元件和与期望的延迟元件串联连接的公共延迟元件; 沿着第二路径将参考时钟施加到第一延迟元件和公共延迟元件; 测量所述公共延迟元件的输出处的所述第一和第二路径之间的延迟差; 以及基于所测量的延迟差来调整所述延迟元件的延迟。可以在电压控制的延迟环路中对每个延迟元件重复修整方法。

7. 发明授权

US08067966B2 Voltage controlled delay loop and method with injection point control 有权
标题翻译：电压控制延时回路和注入点控制方法
公开(公告)号：US08067966B2
公开(公告)日：2011-11-29
申请号：US10999900
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。多个延迟元件串联连接，例如循环。在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。

8. 发明申请

US20090108898A1 METHODS AND APPARATUS FOR IMPROVED PHASE SWITCHING AND LINEARITY IN AN ANALOG PHASE INTERPOLATOR 有权
标题翻译：改进的相位切换和模拟相位插值器的线性度的方法和装置
公开(公告)号：US20090108898A1
公开(公告)日：2009-04-30
申请号：US12344047
申请日：2008-12-24
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03H11/16
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位插值器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

9. 发明授权

US07298195B2 Methods and apparatus for improved phase switching and linearity in an analog phase interpolator 失效
标题翻译：用于改善模拟相位内插器中的相位切换和线性度的方法和装置
公开(公告)号：US07298195B2
公开(公告)日：2007-11-20
申请号：US11095771
申请日：2005-03-31
申请人： Ronald L. Freyman , Craig B. Ziemer
发明人： Ronald L. Freyman , Craig B. Ziemer
IPC分类号： H03K5/13
CPC分类号： H03C3/225
摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
摘要翻译：提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位内插器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

10. 发明授权

US4360742A Synchronous binary-counter and programmable rate divider circuit 失效
标题翻译：同步二进制计数器和可编程分频电路
公开(公告)号：US4360742A
公开(公告)日：1982-11-23
申请号：US175054
申请日：1980-08-04
申请人： Ronald L. Freyman
发明人： Ronald L. Freyman
IPC分类号： H03K23/50 , H03K23/66 , H03K21/36 , H03K21/34 , H03K23/22
CPC分类号： H03K23/66 , H03K23/50
摘要： An MOS parallel carry synchronous binary counter/clock rate divider circuit has a chain of simultaneously clocked T flip-flop interconnected by an improved enable logic circuit having a plurality of identical carry stages each associated with a different flip-flop except the first and last flip-flop of the chain. Each carry stage has an input terminal connected to the inverted enable input of its associated flip-flop, an output terminal connected to the inverted enable input of the next flip-flop in the chain, a transmission gate transistor having a conduction channel connected in series between the input and output terminals and a gate connected to the normal output of the associated flip-flop, and a depletion mode load transistor having a conduction channel connected between a VDD power supply terminal and the output terminal and a gate connected to the output terminal. The carry stage associated with the first flip-flop comprises an inverter having an input connected to the normal output of the first flip-flop and an output connected to the inverted enable input of the second flip-flop. The clock rate division signal provided by the output of the last flip-flop in the chain can be made programmable by including a programming network in each carry stage. The programming network comprises one or more transistors having conduction channels coupled in series between the output terminal and ground and having gates responsive to control signals for forcing a logic "0" level on the output terminal.
摘要翻译： MOS并行进位同步二进制计数器/时钟分频器电路具有通过改进的使能逻辑电路互连的同步时钟T触发器链，其具有多个相同的进位级，每个与不同的触发器相关联，除了第一和最后一个翻转链的一角。每个进位级具有连接到其相关联的触发器的反相使能输入的输入端子，连接到链中的下一个触发器的反相使能输入的输出端子，具有串联连接的导通通道的传输栅极晶体管在输入和输出端子之间以及连接到相关联的触发器的正常输出的栅极以及连接在VDD电源端子和输出端子之间的导通沟道的耗尽型负载晶体管和连接到输出端子的栅极。与第一触发器相关联的进位级包括具有连接到第一触发器的正常输出的输入的反相器和连接到第二触发器的反相使能输入的输出。由链中最后一个触发器的输出提供的时钟分频信号可以通过在每个进位阶段中包括一个编程网络来进行可编程。编程网络包括一个或多个晶体管，其具有串联耦合在输出端子和地之间的导通通道，并具有响应控制信号的栅极，用于强制输出端子上的逻辑“0”电平。

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