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1. 发明授权

US5301278A Flexible dynamic memory controller 失效
标题翻译：灵活的动态存储控制器
公开(公告)号：US5301278A
公开(公告)日：1994-04-05
申请号：US873880
申请日：1992-04-23
申请人： Ronald J. Bowater , Steven P. Larky , Joe C. St. Clair , Paolo G. Sidoli
发明人： Ronald J. Bowater , Steven P. Larky , Joe C. St. Clair , Paolo G. Sidoli
IPC分类号： G06F13/16 , G11C7/22 , G11C8/18 , G11C11/4076 , G06F13/10
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/1694 , G11C11/4076 , G11C8/18
摘要： A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.
摘要翻译：灵活的动态存储器控制器，其可操作与动态RAMS具有广泛的操作特性。这些特征包括各种存储器功能的不同操作速度和存储器的使用。在状态机中，使用专用寄存器来控制操作顺序以及必须插入多长时间的延迟。根据在给定时间访问的存储器的类型和请求的来源，存储器控制器动态地确定延迟。

2. 发明授权

US5319395A Pixel depth converter for a computer video display 失效
标题翻译：用于计算机视频显示的像素深度转换器
公开(公告)号：US5319395A
公开(公告)日：1994-06-07
申请号：US54701
申请日：1993-04-28
申请人： Steven P. Larky , Alan W. Peevers , Joe C. St. Clair
发明人： Steven P. Larky , Alan W. Peevers , Joe C. St. Clair
IPC分类号： G09G5/14 , G09G5/393 , G09G1/02
CPC分类号： G09G5/393 , G09G5/14
摘要： A pixel-depth converter for source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth. A packed-pixel-data depacker circuit receives source-pixel data words having a packed-pixel data format from a source-pixel-data memory and transmits the data words depacked-pixel-data-word-component-by-depacked-pixel-data-word-component in accordance with a user selected pixel-depth-conversion scale factor. A pixel-data-conversion-table storage circuit stores selectable depth-altering pixel-data-conversion data in locations having conversion-table read addresses which are associated with values corresponding to the selected pixel-depth-conversion scale factor. The storage circuit includes independently-operable converted-data-read parallel output ports and associated conversion-table read-address input ports. Conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table storage circuit. Stored conversion data can be read in parallel from the associated converted-data-read output ports. Input ports of multiplexers are connected to corresponding terminal subsets of the depacker circuit which are associated with different pixel-depth-conversion scale factor. A conversion-lookup address output port of each multiplexer is connected to an associated read-address input port of the storage circuit. The multiplexer control-signal input ports are connectable to a bus for receiving a scale-factor-selection signal which specifies the desired pixel-depth-conversion scale factor and corresponding depacked-source-pixel-data portions.
摘要翻译：用于源像素数据的像素深度转换器，其具有源目标像素深度与目标像素数据的距离不同于源像素深度的目标像素深度。压缩像素数据去除器电路从源像素数据存储器接收具有压缩像素数据格式的源像素数据字，并且将数据字解码像素数据字分量逐个像素数据存储器，数据字分量根据用户选择的像素深度转换比例因子。像素数据转换表存储电路将可选择的深度改变像素数据转换数据存储在具有与所选择的像素深度转换比例因子对应的值相关联的转换表读取地址的位置中。存储电路包括可独立操作的转换数据读取并行输出端口和相关联的转换表读地址输入端口。转换查找地址可以独立地并行地应用于多个转换表存储电路。存储的转换数据可以从相关联的转换数据读取输出端口并行读取。多路复用器的输入端口连接到与不同像素深度转换比例因子相关联的存储器电路的相应终端子集。每个多路复用器的转换查找地址输出端口连接到存储电路的相关读取地址输入端口。多路复用器控制信号输入端口可连接到总线，用于接收指定期望的像素深度转换比例因子和相应的解码源像素数据部分的比例因子选择信号。

3. 发明授权

US5329613A Apparatus and method for relating a point of selection to an object in a graphics display system 失效
标题翻译：将选择点与图形显示系统中的对象相关联的装置和方法
公开(公告)号：US5329613A
公开(公告)日：1994-07-12
申请号：US58991
申请日：1993-05-06
申请人： Deborah D. Brase , Steven P. Larky , Joe C. St. Clair , Paolo Sidoli
发明人： Deborah D. Brase , Steven P. Larky , Joe C. St. Clair , Paolo Sidoli
IPC分类号： G06F3/153 , G06F3/033 , G06F3/048 , G06T1/60 , G06T11/80 , G06T15/30 , G09G5/36 , G06F15/62
CPC分类号： G06F3/04842 , G06T15/30
摘要： Apparatus and methods for picking three dimensional objects from images depicted on a video display. The displayed objects are selectively rerendered. During such rerendering the object pixels are compared in depth to the data in a Z buffer for determining visibility. The number and size of the objects subject to rerendering by the rasterization processor is constrained by using the front end graphics processor to define object extents and by rerendering only extents which have been clipped to the boundaries of the pick window. The rerendering operation does not alter the three dimensional graphics image stored in and repetitively scanned from the frame buffer. Selection between multiple objects within the pick window can include a weighted comparison using a pick plane memory to store visibility data by object.
摘要翻译：用于从视频显示器上描绘的图像中拾取三维物体的装置和方法。显示的对象被选择性地重新呈现。在这种重新渲染期间，将目标像素与Z缓冲器中的数据进行深度比较以确定可视性。通过使用前端图形处理器来定义对象范围并且仅重新渲染已经被剪辑到选择窗口的边界的范围，限制由光栅化处理器重新渲染的对象的数量和大小。退回操作不会改变存储在帧缓冲器中并重复扫描的三维图形图像。选择窗口内的多个对象之间的选择可以包括使用拾取平面存储器按对象存储可见性数据的加权比较。

4. 发明授权

US5113180A Virtual display adapter 失效
标题翻译：虚拟显示适配器
公开(公告)号：US5113180A
公开(公告)日：1992-05-12
申请号：US183795
申请日：1988-04-20
申请人： Satish Gupta , Steven P. Larky , Alan W. Peevers , Joe C. St. Clair
发明人： Satish Gupta , Steven P. Larky , Alan W. Peevers , Joe C. St. Clair
IPC分类号： G09G1/02 , G06F3/153 , G06F12/08 , G06F12/10 , G09G5/00 , G09G5/14 , G09G5/36 , G09G5/39
CPC分类号： G09G5/36 , G06F12/1081 , G09G5/14 , G06F12/08 , G09G5/39
摘要： A display control such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.

5. 发明授权

US5280616A Logic circuit for task processing 失效
标题翻译：用于任务处理的逻辑电路
公开(公告)号：US5280616A
公开(公告)日：1994-01-18
申请号：US890330
申请日：1992-05-26
申请人： Nicholas D. Butler , Malcolm D. Buttimer , Brian C. Homewood , Steven P. Larky , Roderick M. West , Paolo G. Sidoli
发明人： Nicholas D. Butler , Malcolm D. Buttimer , Brian C. Homewood , Steven P. Larky , Roderick M. West , Paolo G. Sidoli
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/46 , G06F9/48 , G06F11/14 , G06F1/06 , G06F11/00
CPC分类号： G06F9/4881 , G06F9/30043 , G06F9/30141 , G06F9/3851 , G06F9/3861 , G06F9/461 , G06F11/14
摘要： In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.
摘要翻译：在具有时钟状态锁存器和组合逻辑的逻辑电路中，响应于状态锁存器的功能时钟来执行任务的功能处理，状态锁存器被附加地互连以形成可扫描的锁存器链，并且提供任务切换逻辑用于暂停任务通过中断状态锁存器的功能时钟来处理，并且在这种暂停期间扫描状态锁存器，使得可以从状态锁存器或定义任务状态的新内容中保存定义任务状态的状态锁存器的现有内容，状态锁定。本发明提供了一种用于在多处理环境中由逻辑电路执行的切换任务的有效手段。

6. 发明授权

US07047173B1 Analog signal verification using digital signatures 失效
标题翻译：使用数字签名的模拟信号验证
公开(公告)号：US07047173B1
公开(公告)日：2006-05-16
申请号：US09631427
申请日：2000-08-03
申请人： Steven P. Larky , Terry D. Little
发明人： Steven P. Larky , Terry D. Little
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or more attributed analog signals.
摘要翻译：一种用于对模拟信号建模的方法，其可以包括（A）检测一个或多个归属的模拟信号，以及（B）通过向所述一个或多个归属的模拟信号中的每一个添加签名来对归属的模拟信号进行建模。

7. 发明授权

US6092210A Device and method for synchronizing the clocks of interconnected universal serial buses 有权
标题翻译：互连通用串行总线时钟同步的装置和方法
公开(公告)号：US6092210A
公开(公告)日：2000-07-18
申请号：US173470
申请日：1998-10-14
申请人： Steven P. Larky , Scott Swindle
发明人： Steven P. Larky , Scott Swindle
IPC分类号： G06F13/40 , G06F1/12
CPC分类号： G06F13/4054
摘要： A USB-to-USB connecting device is provided for interconnecting two independent universal serial buses (USBs) and for synchronizing local device clocks to the data streams of both USBs. To interconnect the USBs, the device may include a separate local clock synchronization mechanism for each USB connected to the device. Each separate local clock synchronization may utilize the same reference clock. A method for interconnecting two USBs is also provided.
摘要翻译： USB-USB连接设备用于互连两个独立的通用串行总线（USB），并用于将本地设备时钟同步到两个USB的数据流。为了互连USB，设备可以为连接到设备的每个USB包括单独的本地时钟同步机制。每个单独的本地时钟同步可以利用相同的参考时钟。还提供了一种用于互连两个USB的方法。

8. 发明授权

US5452412A High performance rasterization engine 失效
标题翻译：高性能光栅化引擎
公开(公告)号：US5452412A
公开(公告)日：1995-09-19
申请号：US109414
申请日：1993-08-19
申请人： Lee E. Johnson, Jr. , Daryl J. Kokoszka , Steven P. Larky , Paolo Sidoli
发明人： Lee E. Johnson, Jr. , Daryl J. Kokoszka , Steven P. Larky , Paolo Sidoli
IPC分类号： G06F3/153 , G06T11/20 , G06T15/83 , G06T15/87 , G06T15/10
CPC分类号： G06T15/83 , G06T11/40 , G06T15/87
摘要： A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.
摘要翻译：一种图形处理器，包括用于提供表示图形图像的三角形图元和线图元的接口，用于接收线图元和用于渲染线图元的线抽屉，以及用于从界面接收三角形图元并用于从其提供线图元的三角形插值器其中所述接口包括用于存储图形图像线原语的寄存器，并且用于选择性地将所存储的线原语提供给线抽屉。

9. 发明授权

US4956638A Display using ordered dither 失效
标题翻译：使用有序抖动显示
公开(公告)号：US4956638A
公开(公告)日：1990-09-11
申请号：US245857
申请日：1988-09-16
申请人： Steven P. Larky , Bruce D. Lucas , Daniel H. McCabe , Todd K. Rodgers
发明人： Steven P. Larky , Bruce D. Lucas , Daniel H. McCabe , Todd K. Rodgers
IPC分类号： G09G5/00 , G06T5/00 , G09G3/20 , G09G5/02 , G09G5/06 , H04N1/41 , H04N1/64
CPC分类号： H04N1/648 , G09G5/02 , G09G3/2051
摘要： A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.

10. 发明授权

US4910687A Bit gating for efficient use of RAMs in variable plane displays 失效
标题翻译：位选通以在可变平面显示器中高效使用RAM
公开(公告)号：US4910687A
公开(公告)日：1990-03-20
申请号：US116104
申请日：1987-11-03
申请人： Nicholas D. Butler , Brian C. Homewood , Steven P. Larky
发明人： Nicholas D. Butler , Brian C. Homewood , Steven P. Larky
IPC分类号： G06F3/153 , G06T9/00 , G09G1/00 , G09G1/02 , G09G5/00 , G09G5/36 , G09G5/39 , G09G5/395
CPC分类号： G09G5/395
摘要： Apparatus for serializing 2.sup.M parallel outputs of an all points addressable memory into successive data groups, with each data group corresponding to a respective value for a pixel in an image, wherein the bit-length of the pixel value is selectable. The apparatus includes a gate circuit having 2.sup.M parallel input junctions connected to the outputs of the memory and 2.sup.N output junctions. The gate circuit selectively converts each set of 2.sup.M parallel inputs at the input junctions in to 2.sup.M-n successive data groups, with each group having a bit-length of 2.sup.n bits. Each such group is transmitted to 2.sup.n of the 2.sup.N output junctions. A communication element conveys to the gate circuit a signal which controls the bit-length 2.sup.n of the data groups, wherein n is an integer 1.ltoreq.n.ltoreq.N.ltoreq.M.

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