专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06671831B1 Fault tolerant USB method and apparatus 有权
标题翻译：容错USB方法和设备
公开(公告)号：US06671831B1
公开(公告)日：2003-12-30
申请号：US09592201
申请日：2000-06-13
申请人： Ronald H. Sartore , Steven P. Larky
发明人： Ronald H. Sartore , Steven P. Larky
IPC分类号： G06F1314
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/0757 , G06F11/076 , G06F13/4278
摘要： One aspect of the present invention concerns an apparatus comprising a circuit that may be configured to present a connection signal. The connection signal may be configured to automatically disconnect and reconnect a peripheral device from a host in response to one or more errors. In another aspect of the present invention the connection signal may be configured to shift a configuration of a peripheral device in response to one or more errors.
摘要翻译：本发明的一个方面涉及一种包括可被配置为呈现连接信号的电路的装置。连接信号可以被配置为响应于一个或多个错误而自动断开并重新连接外围设备与主机。在本发明的另一方面，连接信号可以被配置为响应于一个或多个错误来移位外围设备的配置。

2. 发明授权

US06493770B1 System for reconfiguring a peripheral device by downloading information from a host and electronically simulating a physical disconnection and reconnection to reconfigure the device 有权
标题翻译：用于通过从主机下载信息并电子地模拟物理断开和重新连接以重新配置设备来重新配置外围设备的系统
公开(公告)号：US06493770B1
公开(公告)日：2002-12-10
申请号：US09878488
申请日：2001-06-11
申请人： Ronald H. Sartore , Steven P. Larky
发明人： Ronald H. Sartore , Steven P. Larky
IPC分类号： G06F13368
CPC分类号： G06F13/10
摘要： A system and method for reconfiguring a peripheral device connected by a computer bus and port to a host from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.
摘要翻译：提供了一种用于将由计算机总线和端口连接到主机的外围设备从第一通用配置重新配置到第二制造商特定配置的系统和方法，其中可以电子地复位外围设备的配置。还提供了用于标准化的计算机外围设备总线和端口的外围接口设备，其中模拟外围设备的物理断开和重新连接以重新配置特定外围设备的总线和端口。

3. 发明授权

US06839778B1 Speed power efficient USB method 有权
标题翻译：速度高效USB方式
公开(公告)号：US06839778B1
公开(公告)日：2005-01-04
申请号：US09590831
申请日：2000-06-09
申请人： Ronald H. Sartore , Steven P. Larky , Cathal G. Phelan
发明人： Ronald H. Sartore , Steven P. Larky , Cathal G. Phelan
IPC分类号： G06F13/10 , G06F13/40
CPC分类号： G06F13/4081 , Y02D10/14 , Y02D10/151
摘要： An apparatus comprising a peripheral device and a host device. The peripheral device may be connected to the host device. The speed of the peripheral device may be adjusted in response to one or more predetermined conditions.

4. 发明授权

US6012103A Bus interface system and method 失效
标题翻译：总线接口系统和方法
公开(公告)号：US6012103A
公开(公告)日：2000-01-04
申请号：US886923
申请日：1997-07-02
申请人： Ronald H. Sartore , Steven P. Larky
发明人： Ronald H. Sartore , Steven P. Larky
IPC分类号： G06F13/10 , G06F13/368
CPC分类号： G06F13/10
摘要： A system and method for reconfiguring a peripheral device connected by a computer bus and port to a host from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.
摘要翻译：提供了一种用于将由计算机总线和端口连接到主机的外围设备从第一通用配置重新配置到第二制造商特定配置的系统和方法，其中可以电子地复位外围设备的配置。还提供了用于标准化的计算机外围设备总线和端口的外围接口设备，其中模拟外围设备的物理断开和重新连接以重新配置特定外围设备的总线和端口。

5. 发明授权

US06625761B1 Fault tolerant USB method and apparatus 有权
公开(公告)号：US06625761B1
公开(公告)日：2003-09-23
申请号：US09592206
申请日：2000-06-13
申请人： Ronald H. Sartore , Steven P. Larky
发明人： Ronald H. Sartore , Steven P. Larky
IPC分类号： H02H306
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/1441
摘要： One aspect of the present invention concerns an apparatus comprising a circuit that may be configured to present a connection signal. The connection signal may be configured to automatically disconnect and reconnect a peripheral device from a host in response to one or more errors. In another aspect of the present invention the connection signal may be configured to shift a configuration of a peripheral device in response to one or more errors.

6. 发明授权

US06249825B1 Universal serial bus interface system and method 有权
标题翻译：通用串行总线接口系统及方法
公开(公告)号：US06249825B1
公开(公告)日：2001-06-19
申请号：US09476923
申请日：2000-01-04
申请人： Ronald H. Sartore , Steven P. Larky
发明人： Ronald H. Sartore , Steven P. Larky
IPC分类号： G06F13368
CPC分类号： G06F13/10
摘要： A system for reconfiguring a peripheral device having a first configuration connected by a computer bus and a port to a host computer. The system comprises a first circuit and a second circuit. The first circuit may be configured to download information for a second configuration from the host computer into the peripheral device over the computer bus. The second circuit may be configured to electronically simulate, over the computer bus, a physical disconnection and reconnection of the peripheral device to reconfigure the peripheral device to the second configuration.
摘要翻译：一种用于重新配置具有由计算机总线和端口连接到主机的第一配置的外围设备的系统。该系统包括第一电路和第二电路。第一电路可以被配置为通过计算机总线从主计算机将用于第二配置的信息下载到外围设备中。第二电路可以被配置为通过计算机总线电子地模拟外围设备的物理断开和重新连接以将外围设备重配置到第二配置。

7. 发明申请

US20110125953A1 FLASH MEMORY ORGANIZATION FOR REDUCED FAILURE RATE 有权
标题翻译：用于降低故障率的闪存组织
公开(公告)号：US20110125953A1
公开(公告)日：2011-05-26
申请号：US12624348
申请日：2009-11-23
申请人： Ronald H. Sartore
发明人： Ronald H. Sartore
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0638 , G06F3/0616 , G06F3/0646 , G06F3/0679 , G06F12/0246 , G06F2212/1032 , G06F2212/7208
摘要： A memory system includes logic to distribute bits of a data word from a first memory across multiple pages of a flash memory.
摘要翻译：存储器系统包括逻辑，以分配来自闪存的多个页面上的第一存储器的数据字的位。

8. 发明申请

US20110072302A1 SOLID STATE MEMORY CARTRIDGE WITH WEAR INDICATION 有权
标题翻译：具有耐磨指示的固态存储器盒
公开(公告)号：US20110072302A1
公开(公告)日：2011-03-24
申请号：US12566178
申请日：2009-09-24
申请人： Ronald H. Sartore
发明人： Ronald H. Sartore
IPC分类号： G06F11/20 , G06F12/14 , G06F11/32 , G06F11/34 , G06F11/00 , G06F12/00
CPC分类号： G06F11/327 , G11C16/349
摘要： A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.
摘要翻译：描述了包括非易失性存储器的存储器盒。盒式磁带还包括将存储器操作集中在非易失性存储器的特定区域上的逻辑，以使集中区域以相对于非集中区域的加速速率磨损，以及跟踪非易失性存储器上的磨损的逻辑，导致从一个或两个擦除和写入。

9. 发明申请

US20080150905A1 Feedback mechanism for user detection of reference location on a sensing device 有权
标题翻译：用于检测感测设备上参考位置的反馈机制
公开(公告)号：US20080150905A1
公开(公告)日：2008-06-26
申请号：US11645071
申请日：2006-12-21
申请人： Edward L. Grivna , David G. Wright , Ronald H. Sartore
发明人： Edward L. Grivna , David G. Wright , Ronald H. Sartore
IPC分类号： G06F3/041
CPC分类号： G06F3/016 , G06F3/0227 , G06F3/044 , G06F2203/04111
摘要： An apparatus and method for providing an active feedback of a position of a conductive object, manipulated by a user on a sensing device, to allow detection of a reference location on the sensing device by the user. The apparatus may include a sensing device to detect a presence of a conductive object, manipulated by a user on the sensing device, a processing device coupled to the sensing device, the processing device to determine a position of the conductive object on the sensing device, and a feedback mechanism coupled to the processing device to provide an active feedback to the user to allow detection of a reference location on the sensing device by the user.
摘要翻译：一种用于提供由感测装置上的用户操纵的导电物体的位置的有效反馈的装置和方法，以允许用户检测所述感测装置上的参考位置。该装置可以包括用于检测由感测装置上的用户操纵的导电物体的存在的感测装置，耦合到感测装置的处理装置，处理装置，用于确定导电物体在感测装置上的位置，以及耦合到处理设备的反馈机制，以向用户提供主动反馈以允许用户检测感测设备上的参考位置。

10. 发明授权

US06347357B1 Enhanced DRAM with embedded registers 失效
标题翻译：具有嵌入式寄存器的增强型DRAM
公开(公告)号：US06347357B1
公开(公告)日：2002-02-12
申请号：US09182994
申请日：1998-10-30
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
IPC分类号： G06F1200
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式