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    • 1. 发明申请
      US20090122619A1 Enhanced DRAM with Embedded Registers 审中-公开
    • Enhanced DRAM with Embedded Registers
    • 具有嵌入式寄存器的增强型DRAM
    • US20090122619A1
    • 2009-05-14
    • US12116097
    • 2008-05-06
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
    • G11C7/00 , G11C8/00
    • G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
    • An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
    • 增强型DRAM包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US07370140B2 Enhanced DRAM with embedded registers 失效
    • Enhanced DRAM with embedded registers
    • 具有嵌入式寄存器的增强型DRAM
    • US07370140B2
    • 2008-05-06
    • US09962287
    • 2001-09-24
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
    • G06F12/00
    • G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
    • An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
    • 增强型DRAM包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US5721862A Enhanced DRAM with single row SRAM cache for all device read operations 失效
    • Enhanced DRAM with single row SRAM cache for all device read operations
    • 具有单行SRAM缓存的增强型DRAM，用于所有器件读取操作
    • US5721862A
    • 1998-02-24
    • US460665
    • 1995-06-02
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
    • G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G06F12/00
    • G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
    • An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register. Additionally, the row registers/memory cache is sized to contain a row of data of the DRAM array. Furthermore, a single column decoder addresses corresponding locations in both the memory cache and the DRAM array. And finally, all reads are only from the memory cache.
    • 增强型DRAM包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。 另外，行寄存器/存储器高速缓冲存储器的大小可以包含DRAM阵列的一行数据。 此外，单列解码器解决存储器高速缓存和DRAM阵列中的相应位置。 最后，所有的读取只能从内存缓存中读取。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5699317A Enhanced DRAM with all reads from on-chip cache and all writers to memory array 失效
    • Enhanced DRAM with all reads from on-chip cache and all writers to memory array
    • 增强型DRAM，具有从片上缓存和所有写入器到存储器阵列的所有读取
    • US5699317A
    • 1997-12-16
    • US319289
    • 1994-10-06
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
    • G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G11C11/409
    • G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
    • An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
    • 增强型动态随机存取存储器（DRAM）包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以静态随机存取存储器（SRAM）速度读取高速缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US06347357B1 Enhanced DRAM with embedded registers 失效
    • Enhanced DRAM with embedded registers
    • 具有嵌入式寄存器的增强型DRAM
    • US06347357B1
    • 2002-02-12
    • US09182994
    • 1998-10-30
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
    • G06F1200
    • G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
    • An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
    • 增强型DRAM包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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