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1. 发明授权

US07030669B2 Circuit to linearize gain of a voltage controlled oscillator over wide frequency range 有权
标题翻译：电路在宽频率范围内线性化压控振荡器的增益
公开(公告)号：US07030669B2
公开(公告)日：2006-04-18
申请号：US10779891
申请日：2004-02-17
申请人： Ronald B. Hulfachor , James J. McDonald, II
发明人： Ronald B. Hulfachor , James J. McDonald, II
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03L7/0995
摘要： A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.
摘要翻译：示出了使用多个延迟级的压控振荡器电路，其中最后阶段环回到第一级。通过对一个或多个电容器充电来形成每一级延迟。该电路使用有源元件，显示出控制电压和所得电流之间的平方律关系。电流最终用于对延迟电容器充电。净效应是VCO频率和输入控制电压的线性关系。通过使用平方律电流源来提供线性关系的范围，以提供适当的电流，当其他有源器件不再支持平方律关系时，延伸线性范围。此外，双极性器件用于补偿FET器件的温度和批次处理效果。

2. 发明授权

US06940356B2 Circuitry to reduce PLL lock acquisition time 有权
标题翻译：电路减少PLL锁定采集时间
公开(公告)号：US06940356B2
公开(公告)日：2005-09-06
申请号：US10780493
申请日：2004-02-17
申请人： James J. McDonald, II , Ronald B. Hulfachor
发明人： James J. McDonald, II , Ronald B. Hulfachor
IPC分类号： H03L7/089 , H03L7/095 , H03L7/107 , H03L7/18 , H03L7/00
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/095 , H03L7/18 , Y10S331/02
摘要： A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.
摘要翻译：使用多个并联电荷泵描述了锁相环PLL，当并联锁相时，该电荷泵被选择性地禁用。描述了使得能够将参考电流馈送到并联电荷泵的锁定检测电路。来自相位检测器的误差信号被布置为在锁定检测器中被平均的UP和DOWN信号。当平均误差较大时，所有参考电流都会提供提供高回路增益的电荷泵，以减少锁定时间。随着锁变得更近，选择性参考电流被禁用以减小环路增益，从而进行平滑过渡到锁定。选择性地将电流切换到通常在PLL电路中的电荷泵之后的低通滤波器中，通过低通滤波器的操作自动降低开关噪声。

3. 发明授权

US06794945B2 PLL for clock recovery with initialization sequence 有权
标题翻译： PLL用于具有初始化序列的时钟恢复
公开(公告)号：US06794945B2
公开(公告)日：2004-09-21
申请号：US10412448
申请日：2003-04-11
申请人： James J. McDonald, II , Ronald B. Hulfachor , Jim Wunderlich
发明人： James J. McDonald, II , Ronald B. Hulfachor , Jim Wunderlich
IPC分类号： H03L706
CPC分类号： H03L7/0891 , H03L7/095 , H03L7/0995 , H03L7/10 , H03L2207/14 , H04L7/033 , H04L7/044 , H04L7/10
摘要： A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
摘要翻译：使用锁相环电路来提供从串行数据流中进行数据位恢复的定时时钟。该系统锁定到SYNC信号，优选地是具有等于完全成帧的串行数据字的时间的周期的低频百分之五十的占空比方波。当检测到启动信号转换时，系统被阻止试图锁定到数据信号边沿转换。但是，该系统提供适合于在各个数据位中计时的信号。

4. 发明授权

US06756826B1 Method of reducing the propagation delay and process and temperature effects on a buffer 失效
标题翻译：降低传播延迟和缓冲液过程和温度影响的方法
公开(公告)号：US06756826B1
公开(公告)日：2004-06-29
申请号：US10460075
申请日：2003-06-12
申请人： Christian Klein , James J. McDonald, II
发明人： Christian Klein , James J. McDonald, II
IPC分类号： H03B100
CPC分类号： H03K19/01721 , H03K17/164
摘要： A buffer circuit with slow output edges is described. Pulsed higher value currents are driven from one shot timing circuits to inject a pulse of current into the control gate of the buffer's output MOSFET to speed up the beginning of the turning on or the turning off of the output MOSFT. When the beginning and turning on and off is reached lower value current sources continue to drive the gate of the output MOSFET. In one embodiment, one shots are triggered from the rising and falling edges of the input signal. The effect of the higher value current pulses is to reduce the circuit delay through the buffer. Also, the pulse width can be designed as temperature sensitive, and supply voltage sensitive so as to maintain the buffer circuit delay as substantially constant as temperature, supply voltage and process variation occur.
摘要翻译：描述具有缓慢输出边缘的缓冲电路。脉冲更高值的电流由单稳定时电路驱动，以将脉冲电流注入缓冲器输出MOSFET的控制栅极，以加速导通开始或关闭输出MOSFT。当达到开始和接通和关断时，电流源继续驱动输出MOSFET的栅极。在一个实施例中，从输入信号的上升沿和下降沿触发一次。较高值电流脉冲的影响是减小通过缓冲器的电路延迟。此外，脉冲宽度可以设计为温度敏感，并且电源电压敏感，以便保持缓冲器电路的延迟基本上恒定，因为温度，电源电压和工艺变化发生。

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