会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Memory controller and interface
    • 内存控制器和接口
    • US06681285B1
    • 2004-01-20
    • US09626464
    • 2000-07-26
    • Arthur Y. Ng
    • Arthur Y. Ng
    • G06F1336
    • G06F13/1605H04N5/44504H04N21/4263H04N21/4316H04N21/435H04N21/4435H04N21/482
    • A memory controller is provided that has an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester. It also has a RAM controller for connection with a RAM connected to the memory data and address buses and/or a ROM controller for connection with a ROM connected to the memory data and address buses. Each such RAM controller and/or ROM controller are connected to the access priority arbiter with one or more control lines. The access priority arbiter receives access requests on one or more of the requester buses and grants access to the memory address and data bus to one requester bus at any one time based on logic internal to the access priority arbiter.
    • 提供了一种存储器控制器,其具有访问优先级仲裁器,其具有存储器地址总线和用于与一个或多个存储器和多个请求总线连接的存储器数据总线,每个请求总线用于连接到存储器请求器。 它还具有用于与连接到存储器数据和地址总线的RAM连接的RAM控制器和/或用于与连接到存储器数据和地址总线的ROM连接的ROM控制器。 每个这样的RAM控制器和/或ROM控制器通过一个或多个控制线连接到访问优先仲裁器。 访问优先级仲裁器在一个或多个请求总线上接收访问请求,并且基于访问优先级仲裁器内部的逻辑在任何一个时间允许访问存储器地址和数据总线到一个请求总线。