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1. 发明授权

US07429001B2 Label identification system and coding method suited therefor 失效
标题翻译：标签识别系统及其编码方法
公开(公告)号：US07429001B2
公开(公告)日：2008-09-30
申请号：US10504376
申请日：2003-02-12
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G06K19/06 , G06K7/08 , H04Q5/22
CPC分类号： G06K7/10336 , G06K7/086 , G06K19/067
摘要： The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.
摘要翻译：本发明涉及一种标签识别系统，包括发送接收单元和识别标签，识别信息以数字识别信息字的形式存储在其上。使用聚合物技术预制的电路装置形式的识别标签上的电路的提供，并且随后通过导体迹线的胶印印刷识别信息，能够提供涉及在廉价大规模生产中能量消耗最小化。识别信息处理的大部分被传送到发送 - 接收单元。

2. 发明申请

US20070085582A1 ELECTRONIC COMPONENT WITH ID TAGS 有权
标题翻译：具有ID标签的电子组件
公开(公告)号：US20070085582A1
公开(公告)日：2007-04-19
申请号：US10562458
申请日：2004-06-30
申请人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： H03K7/08
CPC分类号： G06K19/0723
摘要： The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.
摘要翻译：本发明涉及可以通过交流电压操作的电子部件。所述组件包括具有相同功能的至少一个输入，至少一个输出和一对电子子部件。电子部件的输入端以相同的功能耦合到电子子部件的相应输入端，并且电子部件的输出耦合到所述电子部件的相应输出端，组件。此外，电子部件被配置为使得在交流电压的第一半波期间可以拾取一对功能相同的电子部件中的第一子部件的至少一个输出信号的一个输出信号，而一对功能相同的电子对的第二子分量的一个输出信号可以在交流电压的第二个半波期间被拾取。

3. 发明授权

US06611614B1 Image acquisition apparatus 有权
标题翻译：图像采集装置
公开(公告)号：US06611614B1
公开(公告)日：2003-08-26
申请号：US09597350
申请日：2000-06-19
申请人： Stefan Jung , Roland Thewes , Werner Weber
发明人： Stefan Jung , Roland Thewes , Werner Weber
IPC分类号： G06K900
CPC分类号： G06K9/00067 , G06K9/00973 , G06K9/56 , G06T5/20
摘要： Sensor elements are arranged in a hexagonal grid. A processor element in the form of a primitive automaton is assigned to each of the sensor elements in the grid. The processor elements are set up to perform algorithms which enable lines of a fingerprint to be simplified such that characteristic minutiae of the fingerprint (endings and branchings of the lines) can be extracted. The processor elements are embodied using CMOS/Neuron MOS threshold value logic or using CMOS/NMOS pass transistor logic. The image grid can be read out via read-out circuits as a matrix.
摘要翻译：传感器元件布置在六边形网格中。原始自动机形式的处理器元件被分配给网格中的每个传感器元件。处理器元件被设置为执行能够简化指纹行的算法，使得可以提取指纹的特征细节（结尾和分支）。处理器元件使用CMOS /神经元MOS阈值逻辑或使用CMOS / NMOS传输晶体管逻辑来实现。图像网格可以通过读出电路作为矩阵读出。

4. 发明授权

US06490192B2 Device for evaluating cell resistances in a magnetoresistive memory 有权
公开(公告)号：US06490192B2
公开(公告)日：2002-12-03
申请号：US09968575
申请日：2001-10-01
申请人： Roland Thewes , Werner Weber
发明人： Roland Thewes , Werner Weber
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array having memory cells with cell resistors. The memory cell array further has reference cells with reference cell resistors. The memory cell array is configured such that for testing a respective cell resistor in each case two of the reference cell resistors nearest the respective cell resistor and the reference cell are simultaneously connected to a common word line voltage. A first feedback amplifier together with the two reference cell resistors form a summing amplifier. A second feedback amplifier together with the respective cell resistor form an amplifier having an equivalent gain as the summing amplifier. A comparator is connected to the summing amplifier and the amplifier. The comparator has an output supplying an evaluation signal dependent on the respective cell resistor.

5. 发明授权

US5818112A Arrangement for capacitive signal transmission between the chip layers of a vertically integrated circuit 失效
标题翻译：在垂直集成电路的芯片层之间的电容信号传输的布置
公开(公告)号：US5818112A
公开(公告)日：1998-10-06
申请号：US549201
申请日：1995-10-27
申请人： Werner Weber , Stefan Kuehn , Michael Kleiner , Roland Thewes
发明人： Werner Weber , Stefan Kuehn , Michael Kleiner , Roland Thewes
IPC分类号： H01L27/04 , H01L21/822 , H01L23/48 , H01L23/538 , H01L25/065 , H03K3/356 , H03K3/3565 , H01L29/00 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/48 , H01L23/481 , H03K3/356017 , H03K3/356113 , H03K3/3565 , H01L2225/06527 , H01L2924/0002
摘要： In an arrangement for signal transmission between chip layers of a vertically integrated circuit, a defined, capacitive signal transmission ensues between a part of the vertically integrated circuit in one chip layer and a further part of the vertically integrated circuit in a further chip layer by means of a coupling capacitance. Particularly given high connection densities, a large number of freely placeable and reliable vertical signal connections can be produced directly from the inside of one chip layer to the inside of a neighboring chip layer without extremely high demands being made on the adjustment of the chip layers relative to one another and on the surface planarity of the individual chip layers.
摘要翻译：在用于垂直集成电路的芯片层之间的信号传输的布置中，在一个芯片层中的垂直集成电路的一部分与垂直集成电路的另一部分之间，通过装置的耦合电容。特别是给定的高连接密度，可以从一个芯片层的内部到相邻的芯片层的内部直接产生大量可自由放置和可靠的垂直信号连接，而对芯片层相对的调整没有非常高的要求并且在各个芯片层的表面平面度上。

6. 发明授权

US5701037A Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit 失效
标题翻译：垂直集成电路芯片层之间的电感信号传输布置
公开(公告)号：US5701037A
公开(公告)日：1997-12-23
申请号：US549068
申请日：1995-10-27
申请人： Werner Weber , Stefan Kuehn , Michael Kleiner , Roland Thewes
发明人： Werner Weber , Stefan Kuehn , Michael Kleiner , Roland Thewes
IPC分类号： H01L21/822 , H01L23/48 , H01L23/538 , H01L25/065 , H01L27/00 , H01L27/04 , H01L23/52 , H01L29/40
CPC分类号： H01L23/48 , H01L25/0657 , H01L2225/06513 , H01L2225/06531 , H01L2924/0002
摘要： In an arrangement for signal transmission between chip layers of a vertically integrated circuit, a defined, inductive signal transmission ensues between a part of the vertically integrated circuit in one chip layer and a further part of the vertically integrated circuit in a further chip layer by means of a coupling inductance formed by respective coils in the two layers. Particularly given high connection densities, a large number of freely placeable and reliable vertical signal connections can be produced directly from the inside of one chip layer to the inside of a neighboring chip layer without extremely high demands being made on the adjustment of the chip layers relative to one another and on the surface planarity of the individual chip layers.
摘要翻译：在用于垂直集成电路的芯片层之间的信号传输的布置中，在一个芯片层中的垂直集成电路的一部分和垂直集成电路的另一部分之间，通过装置进一步确定了感应信号传输由两层中的各个线圈形成的耦合电感。特别是给定的高连接密度，可以从一个芯片层的内部到相邻的芯片层的内部直接产生大量可自由放置和可靠的垂直信号连接，而对芯片层相对的调整没有非常高的要求并且在各个芯片层的表面平面度上。

7. 发明授权

US07817037B2 Electronic component with ID tags 有权
标题翻译：具有ID标签的电子元件
公开(公告)号：US07817037B2
公开(公告)日：2010-10-19
申请号：US10562458
申请日：2004-06-30
申请人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G08B13/14 , H03K7/08
CPC分类号： G06K19/0723
摘要： The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.
摘要翻译：本发明涉及可以通过交流电压操作的电子部件。所述组件包括具有相同功能的至少一个输入，至少一个输出和一对电子子部件。电子部件的输入端以相同的功能耦合到电子子部件的相应输入端，并且电子部件的输出耦合到所述电子部件的相应输出端，组件。此外，电子部件被配置为使得在交流电压的第一半波期间可以拾取一对功能相同的电子部件中的第一子部件的至少一个输出信号的一个输出信号，而一对功能相同的电子对的第二子分量的一个输出信号可以在交流电压的第二个半波期间被拾取。

8. 发明授权

US07283372B2 Circuit element having a first layer of an electrically insulating substrate material and method for manufacturing a circuit element 有权
标题翻译：具有电绝缘基板材料的第一层的电路元件和用于制造电路元件的方法
公开(公告)号：US07283372B2
公开(公告)日：2007-10-16
申请号：US10857635
申请日：2004-05-28
申请人： Werner Weber , Gunter Schmid , Richard J. Luyken , Roland Thewes , Markus Seitz
发明人： Werner Weber , Gunter Schmid , Richard J. Luyken , Roland Thewes , Markus Seitz
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H01L51/0595 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C2213/15 , G11C2213/72 , H01L27/28 , H01L51/005 , H01L51/0053 , H01L51/0062 , H01L51/0077
摘要： Circuit element having a first layer composed of an electrically insulating substrate material, a first electrically conductive material which is in the form of at least one discrete area, such that it is embedded in or applied to the substrate material, a second layer having a second electrically conductive material, and a monomolecular layer, which is composed of electrically active molecules which transports charge carriers, arranged between the first layer and the second layer. The monomolecular layer is immobilized and makes electrical contact with the second layer. Each of the electrically active molecules has a first unit, which is used as an electron donor, a second unit, which is used as an electron acceptor, wherein the electron donor and the electron acceptor form a diode, and at least one redox-active unit, by means of which a variable resistance is formed, arranged between the first unit and the second unit.
摘要翻译：具有由电绝缘衬底材料构成的第一层的电路元件，至少一个离散区域形式的第一导电材料，使得其嵌入衬底材料中或施加到衬底材料上，第二层具有第二层导电材料和单分子层，其由布置在第一层和第二层之间的电荷载流子的电活性分子组成。单分子层被固定并与第二层电接触。每个电活性分子具有用作电子给体的第一单元，用作电子受体的第二单元，其中电子给体和电子受体形成二极管，以及至少一种氧化还原活性单元，其中形成有可变电阻，布置在第一单元和第二单元之间。

9. 发明授权

US06717843B1 Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type 失效
标题翻译：用于写入和读取这种类型的存储器的多价，磁阻写/读存储器和方法
公开(公告)号：US06717843B1
公开(公告)日：2004-04-06
申请号：US10089531
申请日：2002-06-04
申请人： Roland Thewes , Werner Weber , Siegfried Schwarzl
发明人： Roland Thewes , Werner Weber , Siegfried Schwarzl
IPC分类号： G11C1100
CPC分类号： G11C11/5607 , G11C11/161 , G11C2211/5615
摘要： A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.
摘要翻译：多值磁阻读/写存储器以及写入和读取这种存储器的方法。本发明尤其具有一个或多个存储单元，每个存储单元具有两个交叉的电导体，以及包括位于电导体的相交处的磁性层的层系统。存储器的特征在于，层系统被指定为具有两个或更多个磁性层的多层系统，其中至少两个磁性层具有彼此独立设置的磁化方向。此外，可以基于流过电导体的电流来改变各层的磁化方向。

10. 发明授权

US6028803A Read amplifier for semiconductor memory cells with means to compensate threshold voltage differences in read amplifier transistors 有权
标题翻译：用于半导体存储单元的读取放大器，用于补偿读取放大器晶体管中的阈值电压差
公开(公告)号：US6028803A
公开(公告)日：2000-02-22
申请号：US180665
申请日：1998-11-12
申请人： Thomas Kopley , Werner Weber , Roland Thewes
发明人： Thomas Kopley , Werner Weber , Roland Thewes
IPC分类号： G11C11/409 , G11C11/4091 , G11C7/02
CPC分类号： G11C11/4091
摘要： In the read amplifier a mismatch of the inception voltages of cross-coupled transistors (M5, M6) of the read amplifier are compensated by four further transistors (M1 . . . M4), whereby a defined equalizing of the bitlines advantageously takes place with these further transistors simultaneously in what is called the equalize phase. The compensation takes place in that the bitline that is connected with the transistor with the lower inception voltage is charged to a higher level in the pre-load phase. This higher bitline level is switched to the gate of the transistor connected with the other bitline. In the evaluation phase the transistor with the higher inception voltage becomes more strongly conductive. Read amplifiers of this sort are most significant for memory generations beginning at 1 Gbit, since the mismatch due to the variation of the input voltages of the transistors can no longer usefully be solved by a correspondingly large gate surface of the cross-coupled transistors in the read amplifier.
摘要翻译： PCT No.PCT / DE97 / 01027 Sec。 371日期：1998年11月12日 102（e）日期1998年11月12日PCT 1997年5月21日PCT PCT。出版物WO97 / 47010 日期1997年12月11日在读取放大器中，读取放大器的交叉耦合晶体管（M5，M6）的初始电压不匹配由四个另外的晶体管（M1 ... M4）补偿，由此定义的均衡位线有利地与这些另外的晶体管同时进行所谓的均衡相。补偿发生在与初始电压较低的晶体管连接的位线在预加载阶段被充电到更高的电平。该较高的位线电平切换到与另一个位线连接的晶体管的栅极。在评估阶段，具有较高初始电压的晶体管变得更强导电。这种读取放大器对于从1G位开始的存储器代数来说是最重要的，因为由于晶体管的输入电压的变化引起的失配不再有用地被解决了由交叉耦合晶体管的相应大的栅极表面读取放大器。

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