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1. 发明授权

US06967398B2 Module power distribution network 失效
标题翻译：模块配电网络
公开(公告)号：US06967398B2
公开(公告)日：2005-11-22
申请号：US10906152
申请日：2005-02-04
申请人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
发明人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
IPC分类号： H01L23/12 , H01L23/498 , H05K1/00 , H05K1/02 , H01L23/52
CPC分类号： H05K1/0216 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/09701 , H01L2924/15192 , H01L2924/19105 , H01L2924/3011 , H05K1/0231 , H05K1/0298 , H05K2201/09327 , H05K2201/10522 , H05K2201/10734
摘要： A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.
摘要翻译：用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

2. 发明申请

US20050167811A1 MODULE POWER DISTRIBUTION NETWORK 失效
标题翻译：模块电力分配网络
公开(公告)号：US20050167811A1
公开(公告)日：2005-08-04
申请号：US10906152
申请日：2005-02-04
申请人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
发明人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
IPC分类号： H01L23/12 , H01L23/498 , H05K1/00 , H05K1/02 , H01L23/495
CPC分类号： H05K1/0216 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/09701 , H01L2924/15192 , H01L2924/19105 , H01L2924/3011 , H05K1/0231 , H05K1/0298 , H05K2201/09327 , H05K2201/10522 , H05K2201/10734
摘要： A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.
摘要翻译：用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

3. 发明授权

US06774836B2 Method for delta-noise reduction 失效
标题翻译：减少降噪的方法
公开(公告)号：US06774836B2
公开(公告)日：2004-08-10
申请号：US10462529
申请日：2003-06-16
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
IPC分类号： H04L1702
CPC分类号： G05F1/46
摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.
摘要翻译：一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案最小化每个活动单位设备当定期运行时的当前需求。选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

4. 发明授权

US5956563A Method for reducing a transient thermal mismatch 失效
标题翻译：降低瞬态热失配的方法
公开(公告)号：US5956563A
公开(公告)日：1999-09-21
申请号：US765525
申请日：1997-01-09
申请人： Erich Klink , Dietmar Schmunkamp , Helmut Weber , Roland Frech , Bernd Garben , Hubert Harrer
发明人： Erich Klink , Dietmar Schmunkamp , Helmut Weber , Roland Frech , Bernd Garben , Hubert Harrer
IPC分类号： G06F1/20 , G06F1/10 , H01L21/321 , H01L21/60 , H01L23/34 , H03L7/06 , H01L21/00
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/09701
摘要： The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.
摘要翻译： PCT No.PCT / EP95 / 02152 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT Filed June 6，1995 PCT Pub。公开号WO96 / 39714 PCT 日期：1996年12月12日本发明涉及一种降低彼此机械接触的第一部件和第二部件之间的瞬态热失配的方法。第一部件的温度由其消耗的能量的量来控制。根据输入到第一组件的数据模式来控制消耗的能量，这导致组件内的一定数量的门在每个时钟周期内切换。通过根据要切换的栅极的数量确定期望的能量耗散并且相应地布置输入数据模式，可以减少部件之间的热失配。

5. 发明授权

US5812380A Mesh planes for multilayer module 失效
标题翻译：多层模块的网格平面
公开(公告)号：US5812380A
公开(公告)日：1998-09-22
申请号：US765526
申请日：1997-01-09
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Erich Klink
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Erich Klink
IPC分类号： H01L25/00 , H01L23/522 , H01L23/538 , H05K1/03 , H05K1/09 , H05K1/16
CPC分类号： H01L23/5383 , H01L2224/16225 , H01L2924/09701
摘要： A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.
摘要翻译： PCT No.PCT / EP95 / 02194 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT提交1995年6月7日PCT公布。公开号WO96 / 41376 日期1996年12月19日一种用于封装至少一个电子部件50的多层模块。该模块包括多个厚膜层以及允许模块间电容器连接的布线结构45。制造多层模块使得布线结构在厚膜的最上层和第二最上层之间包括部分网格平面46,47,48和49。通过最大化相邻网格平面之间的互感，多层模块中的逻辑噪声降低。

6. 发明授权

US07250812B2 Integrated circuit current regulator 失效
标题翻译：集成电路电流调节器
公开(公告)号：US07250812B2
公开(公告)日：2007-07-31
申请号：US10908289
申请日：2005-05-05
申请人： Roland Frech , Bernd Garben
发明人： Roland Frech , Bernd Garben
IPC分类号： G05F1/10
CPC分类号： G06F1/26
摘要： An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.
摘要翻译：集成电路电流调节器，其基于集成电路的开关活动来补偿所需电流的变化。第一实施例包括具有缩放单元的电压控制片上旁路电路，以将输入电压分成n个分数电压，并且片上电压监视器将片上电源电压的一部分与参考电压进行比较，并且控制相应的片上电源旁路。每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换，以抑制电源噪声。旁路电阻R的值随着片上电源电压的降低而增加，随着电源电压的增加而减小。实现了作为电源电压R（Vdd）特性的电阻，以减少或消除由片上开关活动变化引起的中频电源噪声，同时最大限度地减少额外的片上功耗。

7. 发明申请

US20050248390A1 INTEGRATED CIRCUIT CURRENT REGULATOR 失效
标题翻译：集成电路电流调节器
公开(公告)号：US20050248390A1
公开(公告)日：2005-11-10
申请号：US10908289
申请日：2005-05-05
申请人： Roland Frech , Bernd Garben
发明人： Roland Frech , Bernd Garben
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.
摘要翻译：集成电路电流调节器，其基于集成电路的开关活动来补偿所需电流的变化。第一实施例包括具有缩放单元的电压控制片上旁路电路，以将输入电压分成n个分数电压，并且片上电压监视器将片上电源电压的一部分与参考电压进行比较，并且控制相应的片上电源旁路。每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换，以抑制电源噪声。旁路电阻R的值随着片上电源电压的降低而增加，随着电源电压的增加而减小。实现了作为电源电压R（Vdd）特性的电阻，以减少或消除由片上开关活动变化引起的中频电源噪声，同时最大限度地减少额外的片上功耗。

8. 发明授权

US06665843B2 Method and system for quantifying the integrity of an on-chip power supply network 失效
公开(公告)号：US06665843B2
公开(公告)日：2003-12-16
申请号：US10053197
申请日：2002-01-18
申请人： Roland Frech , Andreas Huber , Erich Klink , Jochen Supper
发明人： Roland Frech , Andreas Huber , Erich Klink , Jochen Supper
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.

9. 发明授权

US06535075B2 Tunable on-chip capacity 失效
标题翻译：可调芯片容量
公开(公告)号：US06535075B2
公开(公告)日：2003-03-18
申请号：US09737929
申请日：2000-12-15
申请人： Roland Frech , Erich Klink , Jochen Supper
发明人： Roland Frech , Erich Klink , Jochen Supper
IPC分类号： H03H701
CPC分类号： H01L27/0805
摘要： The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors. By tuning the total capacity (CSD) of the decoupling capacitors a resonance condition of the resonance loop (40) is met under which a minimum of switching power noise and a minimum switching power consumption is achieved.
摘要翻译：本发明涉及一种用于半导体芯片（10）的可调片上容量电路，该半导体芯片（10）安装在基板（30）上并且包括多个电源去耦电容器（20-23），该电源去耦电容器可通过接通而被选择性地激活或去激活或关闭供电系统。片上检测电路（32）确定片上电源网络的电路特定的负载/卸载频率，响应于检测电路的信号的片上控制装置（28,33）增加或减少片上容量（CSD）通过选择性地激活或去激活电源去耦电容器（20-23）。片外路径阻抗（LMC，RMC），片外容量（CM）和片上容量（CC），包括多个电源去耦电容器（20-23）和寄生片上容量（ CP）形成谐振回路（40），其可通过改变片上电源去耦电容器的总容量（CSD）来调节。通过调谐去耦电容器的总容量（CSD），满足谐振回路（40）的谐振条件，在该谐振回路（40）的谐振条件下达到最小开关功率噪声和最小开关功耗。

10. 发明授权

US07742315B2 Circuit on a printed circuit board 失效
标题翻译：印刷电路板上的电路
公开(公告)号：US07742315B2
公开(公告)日：2010-06-22
申请号：US11282041
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译：本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

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