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1. 发明授权

US07683789B2 Compact omni-directional RF system 有权
标题翻译：紧凑型全向RF系统
公开(公告)号：US07683789B2
公开(公告)日：2010-03-23
申请号：US11073239
申请日：2005-03-04
申请人： Roger Green Stewart , Jyn-Bang Shyu
发明人： Roger Green Stewart , Jyn-Bang Shyu
IPC分类号： G08B13/14
CPC分类号： G06K7/10336 , H01Q21/29 , H01Q25/00
摘要： A radio frequency circuit for summing signals from multiple lobes of an antenna includes circuitry for converting RF signals from lobes of an antenna to baseband signals, and circuitry for summing the baseband signals from the lobes of an antenna.
摘要翻译：用于对来自天线的多个波瓣的信号求和的射频电路包括用于将来自天线的波瓣的RF信号转换为基带信号的电路，以及用于对来自天线的波瓣的基带信号求和的电路。

2. 发明申请

US20060208958A1 Compact omni-directional RF system 有权
标题翻译：紧凑型全向RF系统
公开(公告)号：US20060208958A1
公开(公告)日：2006-09-21
申请号：US11073239
申请日：2005-03-04
申请人： Roger Green Stewart , Jyn-Bang Shyu
发明人： Roger Green Stewart , Jyn-Bang Shyu
IPC分类号： H01Q1/50 , G08B13/14 , G01R29/10
CPC分类号： G06K7/10336 , H01Q21/29 , H01Q25/00
摘要： A radio frequency (RF) system having omindirectional functionality includes a supporting substrate, a circuit coupled to the substrate, and an antenna coupled to the circuit, the antenna having multiple lobes, wherein responses from the lobes are demodulated and combined at baseband. The circuit is positioned over a physical area of a portion of the antenna, the antenna acting as a virtual ground plane for the circuit.
摘要翻译：具有定向功能的射频（RF）系统包括支撑衬底，耦合到衬底的电路和耦合到电路的天线，天线具有多个波瓣，其中来自波瓣的响应在基带被解调和组合。电路位于天线的一部分的物理区域上，该天线用作该电路的虚拟接地平面。

3. 发明授权

US08638144B1 Systems and methods involving phase detection with adaptive locking/detection features 有权
标题翻译：涉及具有自适应锁定/检测特征的相位检测的系统和方法
公开(公告)号：US08638144B1
公开(公告)日：2014-01-28
申请号：US12982839
申请日：2010-12-30
申请人： Jyn-Bang Shyu , Yoshinori Sato , Jae Hyeong Kim , Lee-Lean Shu
发明人： Jyn-Bang Shyu , Yoshinori Sato , Jae Hyeong Kim , Lee-Lean Shu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0814 , H03L7/0816
摘要： Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.
摘要翻译：公开了与控制时钟信号相关联的系统和方法。在一个示例性实现中，提供了延迟锁定环（DLL）和/或延迟/相位检测电路。此外，这种电路可以包括数字相位检测电路，数字延迟控制电路，模拟相位检测电路和模拟延迟控制电路。实现可以包括由于抖动或噪声而防止转换回解锁状态的配置。

4. 发明申请

US20080001667A1 Circuitry For Adaptively Generating And Using A Reference Voltage 有权
标题翻译：用于自适应生成和使用参考电压的电路
公开(公告)号：US20080001667A1
公开(公告)日：2008-01-03
申请号：US11383943
申请日：2006-05-17
申请人： Ta-wei Yang , Larry Farnsley , Jyn-Bang Shyu , Thomas Ching , Robert Olah
发明人： Ta-wei Yang , Larry Farnsley , Jyn-Bang Shyu , Thomas Ching , Robert Olah
IPC分类号： H03F3/45 , H04Q5/22 , H03F3/191 , G08B13/14
CPC分类号： G06K19/0723
摘要： a circuit for an RFID device in one embodiment includes an operational amplifier having a first input, a second input, and an output where the first input receives an incoming signal, arid the second input is coupled to the output via a feedback loop. An operational amplifier for an RFID device according to another embodiment compares an output of the operational amplifier to an incoming baseband signal, A circuit according to another embodiment includes an operational amplifier having a first input, a second input, and an output, wherein the first input receives an incoming signal, and wherein the second input is coupled to the output via a feedback loop. A comparator having one input is coupled to the output of the operational amplifier, another input receiving the incoming signal, and an output for outputting an outgoing signal. Methods for adjusting a filtering characteristic of an operational amplifier are also disclosed.
摘要翻译：在一个实施例中的用于RFID设备的电路包括具有第一输入，第二输入和输出的运算放大器，其中第一输入接收输入信号，并且第二输入经由反馈回路耦合到输出。根据另一实施例的用于RFID设备的运算放大器将运算放大器的输出与输入的基带信号进行比较。根据另一实施例的电路包括具有第一输入，第二输入和输出的运算放大器，其中第一输入接收输入信号，并且其中第二输入经由反馈回路耦合到输出。具有一个输入的比较器耦合到运算放大器的输出端，接收输入信号的另一输入端和用于输出输出信号的输出端。还公开了用于调整运算放大器的滤波特性的方法。

5. 发明申请

US20060273171A1 Differential input circuit with process variation and temperature compensation 有权
公开(公告)号：US20060273171A1
公开(公告)日：2006-12-07
申请号：US11143019
申请日：2005-06-01
申请人： Jyn-Bang Shyu
发明人： Jyn-Bang Shyu
IPC分类号： G06K7/00 , G06K7/08 , G06K19/06
CPC分类号： H03D1/10
摘要： Systems with semiconductor devices that are DC-biased at either their weak inversion (i.e., sub-threshold) region or their strong inversion region. In a preferred embodiment using semiconductor devices (e.g., NMOS, PMOS, etc.), a gate to source voltage (Vgs) is slightly below the threshold voltage (Vtn) of the device. These weakly turned-on semiconductor devices increase the receiving AC sensitivity of an AM-Detector compared to that of a conventional AM-Detector without any DC-biasing. Further, the compensating bias voltage (Vbias) compensates for one or both of the ambient temperature change and the foundry's process variation of the various semiconductor devices.

6. 发明授权

US06266799B1 Multi-phase data/clock recovery circuitry and methods for implementing same 失效
标题翻译：多相数据/时钟恢复电路及其实现方法
公开(公告)号：US06266799B1
公开(公告)日：2001-07-24
申请号：US08967087
申请日：1997-11-10
申请人： Lance K. Lee , Jyn-Bang Shyu , David Y. Wang
发明人： Lance K. Lee , Jyn-Bang Shyu , David Y. Wang
IPC分类号： G06F1750
CPC分类号： H03L7/0991 , H03L7/0814 , H03L7/089 , H03L7/091 , H04L7/0337
摘要： Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder. Preferably, the four predetermined clock phases are continually shifted by the counter if the clock and the data input waveform are not synchronized.
摘要翻译：公开了一种用于高速网络收发器单元的数据/时钟恢复系统。数据/时钟恢复系统包括被配置为接收数据输入波形并产生输出数据的四相采样器电路。一种转换检测电路，被配置为接收由四相采样器电路产生的输出数据。转移检测电路被配置为确定时钟是引导还是滞后数据输入波形。如果时钟由转换检测电路确定为使数据输入波形引导或滞后，则使时钟转换的计数器，使得移位被配置为使时钟和数据输入波形同步。一个从计数器接收控制信号的解码器，使得解码器产生选择信号。数据/时钟恢复系统还包括一个多路复用器，用于响应由解码器产生的选择信号来选择四个预定时钟相位。优选地，如果时钟和数据输入波形不同步，则四个预定时钟相位被计数器连续移位。

7. 发明申请

US20070139159A1 Clock generation circuit 审中-公开
标题翻译：时钟发生电路
公开(公告)号：US20070139159A1
公开(公告)日：2007-06-21
申请号：US11305652
申请日：2005-12-15
申请人： Rohit Mittal , Robert Olah , Jyn-Bang Shyu
发明人： Rohit Mittal , Robert Olah , Jyn-Bang Shyu
IPC分类号： H04Q5/22
CPC分类号： H04L7/046 , H04L7/027 , H04L7/06
摘要： A circuit according to one embodiment of the present invention includes a first frequency to voltage converter for storing a reference voltage based on a frequency of an incoming signal, and a second frequency to voltage converter for storing a second voltage based on the frequency of the incoming signal, the second voltage being a fraction of the reference voltage. A voltage to frequency converter creates a voltage on a node, the voltage repeatedly varying between about the reference voltage and about the second voltage. From this varying signal, a clock signal can be derived.
摘要翻译：根据本发明的一个实施例的电路包括：第一频率 - 电压转换器，用于基于输入信号的频率存储参考电压;以及第二频率 - 电压转换器，用于基于输入的频率存储第二电压信号，第二电压是参考电压的一部分。电压到频率转换器在节点上产生电压，电压在约参考电压和约第二电压之间重复变化。从该变化的信号，可以导出时钟信号。

8. 发明授权

US5675294A Single pin crystal oscillator circuit 失效
标题翻译：单针晶体振荡电路
公开(公告)号：US5675294A
公开(公告)日：1997-10-07
申请号：US582881
申请日：1996-01-04
申请人： Jyn-Bang Shyu , Jin Zhao
发明人： Jyn-Bang Shyu , Jin Zhao
IPC分类号： H03B5/36
CPC分类号： H03B5/364
摘要： A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.
摘要翻译：单引脚集成振荡器电路包括具有可以连接外部晶体的第一输入端子的放大器和从放大器的输出端子接收反馈路径的第二输入端子。通过缓冲器从第一输入端子提供具有相对较大电压摆幅的振荡器输出信号。振荡器在宽范围的电压和工艺变化范围内工作，并且可以接受来自外部晶体的输入信号，或者可以接受具有大约1V的摆幅的任何时钟信号。

9. 发明授权

US5332935A ECL and TTL to CMOS logic converter 失效
标题翻译： ECL和TTL到CMOS逻辑转换器
公开(公告)号：US5332935A
公开(公告)日：1994-07-26
申请号：US45101
申请日：1993-04-12
申请人： Jyn-Bang Shyu
发明人： Jyn-Bang Shyu
IPC分类号： H03K19/0185 , H03K19/094
CPC分类号： H03K19/018528
摘要： A logic converter enables a digital logic product to work with either an ECL signal input or a TTL signal input without any need of modifying or reconfiguring the product. In particular, the logic converter converts digital input signals of a first logic type (for example, ECL) to digital output signals of a third logic type (for example, CMOS). It also converts digital input signals of a second logic type (for example, TTL) to digital output signals of the third logic type. A first operational transconductance amplifier circuit including a first differential amplifier using a differential transistor pair of a first conduction type receives digital input signals of the first logic type and converts the digital input signals to digital output signals of the third logic type. A second operational transconductance amplifier circuit including a second differential amplifier using a differential transistor pair of a second conduction type receives digital input signals of the second logic type and converts the digital input signals to digital output signals of the third logic type. Circuitry causes only one of the first differential amplifier and the second differential amplifier to be active at a time depending on which logic type of digital input signal is being received. The circuitry for causing only one differential amplifier to be active includes a first level shifting circuit connected to the first differential amplifier and a second level shifter circuit connected to the second differential amplifier.
摘要翻译：逻辑转换器使数字逻辑产品能够使用ECL信号输入或TTL信号输入，而无需修改或重新配置产品。特别地，逻辑转换器将第一逻辑类型（例如，ECL）的数字输入信号转换为第三逻辑类型（例如，CMOS）的数字输出信号。它还将第二逻辑类型（例如，TTL）的数字输入信号转换为第三逻辑类型的数字输出信号。包括使用第一导电类型的差分晶体管对的第一差分放大器的第一操作跨导放大器电路接收第一逻辑类型的数字输入信号，并将数字输入信号转换为第三逻辑类型的数字输出信号。包括使用第二导电类型的差分晶体管对的第二差分放大器的第二运算跨导放大器电路接收第二逻辑类型的数字输入信号，并将数字输入信号转换成第三逻辑类型的数字输出信号。根据接收到的数字输入信号的逻辑类型，电路使得第一差分放大器和第二差分放大器中的仅一个一次有效。仅使一个差分放大器有效的电路包括连接到第一差分放大器的第一电平移位电路和连接到第二差分放大器的第二电平移位器电路。

10. 发明授权

US5221890A Reference generator 失效
标题翻译：参考发生器
公开(公告)号：US5221890A
公开(公告)日：1993-06-22
申请号：US851924
申请日：1992-03-16
申请人： Jyn-Bang Shyu , Roubik Gregorian
发明人： Jyn-Bang Shyu , Roubik Gregorian
IPC分类号： G05F1/46 , H03M1/06 , H03M1/74
CPC分类号： H03M1/0604 , G05F1/462 , H03M1/745
摘要： An apparatus for generating a substantially constant voltage control signal using either one of a voltage reference source and a current reference source includes a transistor device responsive to a supply voltage and the voltage control signal to produce a controlled current, an operational amplifier device for generating the voltage control signal in response to the voltage reference source, and a switching device for generating the voltage control signal in response to the current reference source. When the switching device is in one state thereof, an output signal of the operational amplifier device is connected through the transistor device in a closed loop back to an input terminal of the operational amplifier device. When the switching device is in another state thereof, the output signal of the operational amplifier device is connected directly in the closed loop back to an input terminal of the operational amplifier device. In particular, the switching device may be a single-pole, single-throw switch realized using either a pass gate device or a bonding wire option Circuit complexity is therefore reduced.
摘要翻译：用于使用电压参考源和电流参考源中的任一个产生基本上恒定的电压控制信号的装置包括响应于电源电压和电压控制信号以产生受控电流的晶体管器件，用于产生响应于电压参考源的电压控制信号;以及用于响应于当前参考源产生电压控制信号的开关装置。当开关器件处于其一个状态时，运算放大器器件的输出信号通过晶体管器件以闭环回路连接到运算放大器器件的输入端。当开关装置处于其它状态时，运算放大器装置的输出信号直接连接到运算放大器装置的输入端。特别地，开关器件可以是使用通过栅极器件或接合线选项实现的单极单掷开关。因此，电路复杂度降低。

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