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1. 发明授权

US07089135B2 Event based IC test system 失效
标题翻译：基于事件的IC测试系统
公开(公告)号：US07089135B2
公开(公告)日：2006-08-08
申请号：US10150777
申请日：2002-05-20
申请人： Rochit Rajsuman , Shigeru Sugamori , Robert F. Sauer , Hiroaki Yamoto , James Alan Turnquist , Bruce R. Parnas , Anthony Le
发明人： Rochit Rajsuman , Shigeru Sugamori , Robert F. Sauer , Hiroaki Yamoto , James Alan Turnquist , Bruce R. Parnas , Anthony Le
IPC分类号： G01R31/00
CPC分类号： G01R31/31813 , G01R31/318307 , G01R31/318342 , G01R31/31917 , G01R31/31919 , G01R31/31928
摘要： An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.
摘要翻译：一种基于事件的测试系统，用于测试在自动电子设计（EDA）环境下设计的待测IC器件（DUT）。基于事件的测试系统包括事件存储器，用于存储在EDA环境中直接从对于期望的IC的设计数据的模拟得到的事件数据，其中表示每个事件的事件数据形成有指示来自预定点的时间长度的时间索引，指示事件变化类型的事件类型，用于根据事件数据生成测试矢量的事件生成单元，其中由事件类型确定每个矢量的波形，并且通过累积波形的时间指数来确定波形的定时以前的事件，以及用于向DUT提供测试向量并在预定定时评估DUT的响应输出的装置。

2. 发明授权

US06651204B1 Modular architecture for memory testing on event based test system 失效
标题翻译：用于基于事件的测试系统进行内存测试的模块化架构
公开(公告)号：US06651204B1
公开(公告)日：2003-11-18
申请号：US09585831
申请日：2000-06-01
申请人： Rochit Rajsuman , Shigeru Sugamori , Hiroaki Yamoto
发明人： Rochit Rajsuman , Shigeru Sugamori , Hiroaki Yamoto
IPC分类号： G01R3128
CPC分类号： G01R31/31915
摘要： An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.
摘要翻译：基于事件的测试系统具有用于同时测试包括存储器和逻辑器件的多个半导体器件（DUT）的模块化架构。测试系统检测DUT中的功能故障以及物理故障。测试系统包括两个或多个测试器模块，每个测试模块具有多个引脚单元，用于容纳两个或更多个测试器模块的主框架，用于电连接测试器模块和DUT的测试夹具，用于控制整个操作的主计算机的测试系统，以及用于存储用于产生用于测试存储器的存储器测试模式的算法测试模式和软件工具库的数据存储器。存储器测试算法和有关要测试的存储器的设计和配置的信息在存储器测试之前被指定。

3. 发明授权

US06532561B1 Event based semiconductor test system 失效
标题翻译：基于事件的半导体测试系统
公开(公告)号：US06532561B1
公开(公告)日：2003-03-11
申请号：US09406300
申请日：1999-09-25
申请人： James Alan Turnquist , Shigeru Sugamori , Rochit Rajsuman , Hiroaki Yamoto
发明人： James Alan Turnquist , Shigeru Sugamori , Rochit Rajsuman , Hiroaki Yamoto
IPC分类号： G01R3128
CPC分类号： G01R31/31922 , G01R31/31921
摘要： An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.
摘要翻译：基于事件的测试系统被配置为通过向DUT提供测试信号并在选通信号的定时评估DUT的输出来测试被测电子设备（DUT）。基于事件的测试系统包括事件存储器，用于存储以参考时钟周期的整数倍和参考时钟周期的一部分形成的每个事件的定时数据，其中定时数据表示当前事件与参考点之间的时间差，用于产生访问事件存储器的地址数据的地址序列器，用于产生事件开始信号的定时计数和缩放逻辑，用于基于事件开始信号产生每个事件的事件生成单元和指示参考时钟的分数的数据以及用于控制基于事件的测试系统的整体操作的主计算机。

4. 发明授权

US06567941B1 Event based test system storing pin calibration data in non-volatile memory 失效
标题翻译：基于事件的测试系统将引脚校准数据存储在非易失性存储器中
公开(公告)号：US06567941B1
公开(公告)日：2003-05-20
申请号：US09547752
申请日：2000-04-12
申请人： James Alan Turnquist , Rochit Rajsuman , Shigeru Sugamori
发明人： James Alan Turnquist , Rochit Rajsuman , Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G11C29/56 , G01R31/3191 , G01R31/31937
摘要： An event based test system has a cost effective, error free, secure and simple way of managing the calibration data for all of the pin cards used therein. The test system has a large number of test channels for testing a semiconductor device under test (DUT) by applying test patterns to device pins of the DUT through the test channels and examining response outputs of the DUT. The test system includes a plurality of pin cards, each having a plurality of pin units therein to establish a part of the test channels, a non-volatile memory provided within each pin card for storing calibration data for compensating error factors involved in the pin units mounted in the corresponding pin card, and a microprocessor provided within each pin card for managing the calibration data and executing the calibration procedure for all of the pin units in the corresponding pin card, and wherein each pin unit is configured as an event tester in which a test, pattern or a strobe signal is directly generated based on event data stored in an event memory which define any changes from a previous event with reference to a time difference therefrom.
摘要翻译：基于事件的测试系统具有成本效益，无错误，安全和简单的方式来管理其中使用的所有针卡的校准数据。测试系统具有大量用于测试被测半导体器件（DUT）的测试通道，通过测试通道将测试模式应用于DUT的器件引脚并检查DUT的响应输出。测试系统包括多个针卡，每个针卡在其中具有多个针单元以建立测试通道的一部分;提供在每个针卡内的非易失性存储器，用于存储用于补偿引脚单元中涉及的误差因素的校准数据安装在相应的针脚卡中的微处理器，以及设置在每个针卡内的微处理器，用于管理校准数据并对相应的针卡中的所有针单元执行校准程序，并且其中每个针单元配置为事件测试器，其中基于存储在事件存储器中的事件数据直接生成测试，模式或选通信号，所述事件数据定义了与先前事件相关的时间差的任何变化。

5. 发明授权

US06629282B1 Module based flexible semiconductor test system 失效
标题翻译：基于模块的灵活半导体测试系统
公开(公告)号：US06629282B1
公开(公告)日：2003-09-30
申请号：US09434821
申请日：1999-11-05
申请人： Shigeru Sugamori , Rochit Rajsuman
发明人： Shigeru Sugamori , Rochit Rajsuman
IPC分类号： G01R3128
CPC分类号： G01R31/31905 , G01R31/31907
摘要： A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules for easily establishing different semiconductor test systems. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules having different performances, means provided on the test head for electrically connecting the tester modules and a device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus. One type of the performances of the tester module is high speed high timing accuracy while other type of performance is low speed low timing accuracy. Each event tester module includes a tester board which is configured as an event based tester.
摘要翻译：一种半导体测试系统，用于测试半导体器件，特别是涉及具有多种不同类型的测试器模块的半导体测试系统，用于容易地建立不同的半导体测试系统。半导体测试系统包括两个或更多个性能彼此不同的测试器模块，用于容纳两个或更多个具有不同性能的测试器模块的测试头，设置在用于电连接测试器模块的测试头和被测器件以及主计算机，用于通过测试器总线与测试器模块通信来控制测试系统的整体操作。测试器模块的一种性能是高速高定时精度，而其他类型的性能是低速低定时精度。每个事件测试器模块包括被配置为基于事件的测试器的测试器板。

6. 发明授权

US06404218B1 Multiple end of test signal for event based test system 失效
标题翻译：基于事件的测试系统的多端测试信号
公开(公告)号：US06404218B1
公开(公告)日：2002-06-11
申请号：US09559365
申请日：2000-04-24
申请人： Anthony Le , James Alan Turnquist , Rochit Rajsuman , Shigeru Sugamori
发明人： Anthony Le , James Alan Turnquist , Rochit Rajsuman , Shigeru Sugamori
IPC分类号： G01R3102
CPC分类号： G01R31/31937 , G01R31/31921 , G01R31/31922
摘要： An event based test system for testing semiconductor devices under test (DUT). The event based test system is freely configured to a plurality of groups of sin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by generating multiple end of test signals. The event based test system includes a plurality of pin units to be assigned to pins of the DUT, a signal generator for generating an end of test signal for indicating an end of current test which is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.
摘要翻译：用于测试被测半导体器件（DUT）的基于事件的测试系统。基于事件的测试系统被自由地配置到多个单元组，其中每个组能够彼此独立地执行测试操作。每组中的测试的开始和结束定时是通过产生测试信号的多个结果独立地进行的。基于事件的测试系统包括要分配给DUT的引脚的多个引脚单元，用于产生用于指示针对每个引脚单元独立于其它引脚单元生成的当前测试结束的测试信号结束的信号发生器，以及系统控制器，用于通过与每个引脚单元通信来控制基于事件的测试系统的整体操作。每个引脚单元的测试信号的结束由系统控制器指定的条件选择，并且所选择的测试信号的结束提供给系统控制器和其他引脚单元。

7. 发明授权

US06578169B1 Data failure memory compaction for semiconductor test system 失效
标题翻译：半导体测试系统的数据故障记忆压缩
公开(公告)号：US06578169B1
公开(公告)日：2003-06-10
申请号：US09545730
申请日：2000-04-08
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3128
CPC分类号： G01R31/31935 , G11C29/56
摘要： A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.
摘要翻译：用于测试被测半导体器件（DUT）的半导体测试系统能够将故障数据存储在具有小存储器容量的数据故障存储器中。半导体测试系统包括用于在其中存储模式数据以产生要提供给DUT的测试模式的模式存储器，用于评估DUT的输出信号的装置和当其中存在故障时产生故障数据的装置，用于存储故障数据，以及压缩装置，用于在第一测试操作中将模式存储器的多个地址分配给数据故障存储器的单个地址，使得针对模式存储器的每组地址发生的故障数据被存储在数据故障存储器的对应地址，以及仅针对其中检测到故障数据而不进行地址压缩的模式存储器的一组地址执行第二测试操作。

8. 发明授权

US06377065B1 Glitch detection for semiconductor test system 失效
标题翻译：半导体测试系统的毛刺检测
公开(公告)号：US06377065B1
公开(公告)日：2002-04-23
申请号：US09548875
申请日：2000-04-13
申请人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
发明人： Anthony Le , Rochit Rajsuman , James Alan Turnquist , Shigeru Sugamori
IPC分类号： G01R3126
CPC分类号： G01R31/31937 , G01R31/31922
摘要： A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.
摘要翻译：半导体测试系统具有毛刺检测功能，用于检测来自被测器件的输出信号中的毛刺，以准确地评估待测器件（DUT）。半导体测试系统包括用于存储事件数据的事件存储器，用于产生测试图案的事件发生器，用于产生来自事件存储器的事件数据的选通信号和预期模式，用于将测试模式从事件发生器发送到 DUT并接收DUT的输出信号，并通过选通信号的定时对输出信号进行采样，用于将采样输出数据与预期模式进行比较的模式比较器，以及用于从DUT接收输出信号的检测单元通过对输出信号中的边缘数进行计数并比较预期的边缘数量来在输出信号中产生毛刺。

9. 发明授权

US07596730B2 Test method, test system and assist board 失效
标题翻译：测试方法，测试系统和辅助板
公开(公告)号：US07596730B2
公开(公告)日：2009-09-29
申请号：US11394814
申请日：2006-03-31
申请人： Yuya Watanabe , Shigeru Sugamori , Hiroaki Yamoto
发明人： Yuya Watanabe , Shigeru Sugamori , Hiroaki Yamoto
IPC分类号： G01R31/28
CPC分类号： G01R31/31919
摘要： A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory; reading sequentially the written test signal from the memory at the speed higher than that of the test signal generated by the event tester and applying the same to the device under test; acquiring the output signal outputted from the device under test in response to the applied test signal and sequentially writing the same at the speed higher than that of the test signal generated by the event tester; sequentially reading the written output signal from the memory and transmitting the same at the speed lower than that of the output signal outputted from the device under test; and determining pass/fail of the transmitted output signal by the event tester.
摘要翻译：提供了一种通过使用事件测试仪测试被测器件的测试方法。测试方法包括：接收由事件测试器生成的测试信号，并将其应用于被测设备，并将其顺序写入存储器; 以比由事件测试仪产生的测试信号高的速度从存储器顺序读取写入的测试信号，并将其应用于被测器件; 响应于所施加的测试信号获取从被测设备输出的输出信号，并以比由事件测试仪产生的测试信号高的速度顺序写入; 从存储器顺序读取写入的输出信号，并以比从被测器件输出的输出信号的速度低的速度传输; 并通过事件测试器确定发送的输出信号的通过/失败。

10. 发明申请

US20070234146A1 Test method, test system and assist board 失效
标题翻译：测试方法，测试系统和辅助板
公开(公告)号：US20070234146A1
公开(公告)日：2007-10-04
申请号：US11394814
申请日：2006-03-31
申请人： Yuya Watanabe , Shigeru Sugamori , Hiroaki Yamoto
发明人： Yuya Watanabe , Shigeru Sugamori , Hiroaki Yamoto
IPC分类号： G01R31/28
CPC分类号： G01R31/31919
摘要： A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory ; reading sequentially the written test signal from the memory at the speed higher than that of the test signal generated by the event tester and applying the same to the device under test; acquiring the output signal outputted from the device under test in response to the applied test signal and sequentially writing the same at the speed higher than that of the test signal generated by the event tester; sequentially reading the written output signal from the memory and transmitting the same at the speed lower than that of the output signal outputted from the device under test; and determining pass/fail of the transmitted output signal by the event tester.
摘要翻译：提供了一种通过使用事件测试仪测试被测器件的测试方法。测试方法包括：接收由事件测试器生成的测试信号，并将其应用于被测设备，并将其顺序写入存储器; 以比由事件测试仪产生的测试信号高的速度从存储器顺序读取写入的测试信号，并将其应用于被测器件; 响应于所施加的测试信号获取从被测设备输出的输出信号，并以比由事件测试仪产生的测试信号高的速度顺序写入; 从存储器顺序读取写入的输出信号，并以比从被测器件输出的输出信号的速度低的速度传输; 并通过事件测试器确定发送的输出信号的通过/失败。

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