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1. 发明授权

US5796960A Multi-media computer architecture 失效
标题翻译：多媒体计算机体系结构
公开(公告)号：US5796960A
公开(公告)日：1998-08-18
申请号：US452318
申请日：1995-05-26
申请人： Robert P. Bicevskis , Adrian H. Hartog , Gordon Caruk , Michael A. Alford
发明人： Robert P. Bicevskis , Adrian H. Hartog , Gordon Caruk , Michael A. Alford
IPC分类号： G06F13/00
CPC分类号： G06F13/00
摘要： A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.
摘要翻译：计算机系统由主总线和附加的扩展总线，连接到主总线的CPU，连接到主总线或扩展总线之一的外围设备组成，连接到总线的子系统，用于接收控制来自CPU的地址和数据信号，包括图形控制器，数据压缩电路，视频控制器，连接到电路的数据输入端口的存储器和经由具有足以承载视频和图形显示信号的带宽的子系统总线的子系统总线，用于确定哪个控制器被允许访问存储器的第一仲裁器，连接每个控制器的链路总线以及用于向链路总线上的每个控制器和电路提供轮询信号并用于从其接收确认信号的装置，允许在控制器和电路之间交换控制信息。

2. 发明授权

US5696912A Multi-media computer architecture 失效
标题翻译：多媒体计算机体系结构
公开(公告)号：US5696912A
公开(公告)日：1997-12-09
申请号：US684337
申请日：1996-07-19
申请人： Robert P. Bicevskis , Adrian H. Hartog , Gordon Caruk , Michael A. Alford
发明人： Robert P. Bicevskis , Adrian H. Hartog , Gordon Caruk , Michael A. Alford
IPC分类号： G06F3/14 , G06F13/366 , G06F13/38
CPC分类号： G06F3/14 , G06F13/366 , G09G2340/02 , G09G2340/125
摘要： A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.
摘要翻译：计算机系统由主总线和附加的扩展总线，连接到主总线的CPU，连接到主总线或扩展总线之一的外围设备组成，连接到总线的子系统，用于接收控制来自CPU的地址和数据信号，包括图形控制器，数据压缩电路，视频控制器，连接到电路的数据输入端口的存储器和经由具有足以承载视频和图形显示信号的带宽的子系统总线的子系统总线，用于确定哪个控制器被允许访问存储器的第一仲裁器，连接每个控制器的链路总线以及用于向链路总线上的每个控制器和电路提供轮询信号并用于从其接收确认信号的装置，允许在控制器和电路之间交换控制信息。

3. 再颁专利

USRE38610E1 Host CPU independent video processing unit 有权
标题翻译：主机CPU独立视频处理单元
公开(公告)号：USRE38610E1
公开(公告)日：2004-10-05
申请号：US09637824
申请日：2000-08-11
申请人： Sanford S. Lum , Keping Chen , Samuel L. C. Wong , Dwayne R. Bennett , Michael A. Alford
发明人： Sanford S. Lum , Keping Chen , Samuel L. C. Wong , Dwayne R. Bennett , Michael A. Alford
IPC分类号： H04N5262
CPC分类号： G09G5/36
摘要： The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

4. 发明授权

US5793445A Host CPU independent video processing unit 失效
标题翻译：主机CPU独立视频处理单元
公开(公告)号：US5793445A
公开(公告)日：1998-08-11
申请号：US667872
申请日：1996-06-20
申请人： Sanford S. Lum , Keping Chen , Samuel L. C. Wong , Dwayne R. Bennett , Michael A. Alford
发明人： Sanford S. Lum , Keping Chen , Samuel L. C. Wong , Dwayne R. Bennett , Michael A. Alford
IPC分类号： G09G5/36 , G09G5/39 , H04N5/262
CPC分类号： G09G5/36
摘要： The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.
摘要翻译：本发明涉及一种视频显示处理器，包括用于接收要显示的信号的数字输入信号分量的装置，用于将所述分量转换成所需格式的装置，用于缩放和混合所需格式的信号的装置，用于显示或进一步处理的缩放和混合信号，以及用于基本上独立于主机CPU来控制设备的仲裁器和本地定时装置。

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