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1. 发明授权

US08193565B2 Multi-level lateral floating coupled capacitor transistor structures 有权
标题翻译：多电平横向浮动耦合电容晶体管结构
公开(公告)号：US08193565B2
公开(公告)日：2012-06-05
申请号：US12426004
申请日：2009-04-17
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
摘要翻译：半导体器件包括源极区，漏极区，栅极区和漂移区。漂移区域还包括有源漂移区域和无效浮动充电控制（FCC）区域。当电压施加到栅极区域时，有源漂移区域在源极区域和漏极区域之间导通电流。场地形成有源漂移区域以改善击穿电压的无活性FCC区域被垂直地堆叠在漂移区域中并且被有源漂移区域分离。垂直堆叠不活动的FCC区域可以降低导通电阻，同时保持更高的击穿电压。

2. 发明授权

US08580644B2 Multi-level lateral floating coupled capacitor transistor structures 有权
标题翻译：多电平横向浮动耦合电容晶体管结构
公开(公告)号：US08580644B2
公开(公告)日：2013-11-12
申请号：US13461646
申请日：2012-05-01
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
摘要翻译：半导体器件包括具有第一浮动电荷控制结构的有源区和具有第二浮置电荷控制结构的端接区。第二浮动充电控制结构至少是第一浮动控制结构的两倍。

3. 发明申请

US20120211834A1 MULTI-LEVEL LATERAL FLOATING COUPLED CAPACITOR TRANSISTOR STRUCTURES 有权
标题翻译：多级横向浮动耦合电容器晶体管结构
公开(公告)号：US20120211834A1
公开(公告)日：2012-08-23
申请号：US13461646
申请日：2012-05-01
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
摘要翻译：半导体器件包括具有第一浮动电荷控制结构的有源区和具有第二浮置电荷控制结构的端接区。第二浮动充电控制结构至少是第一浮动控制结构的两倍。

4. 发明申请

US20100123171A1 Multi-level Lateral Floating Coupled Capacitor Transistor Structures 有权
标题翻译：多级横向浮动耦合电容晶体管结构
公开(公告)号：US20100123171A1
公开(公告)日：2010-05-20
申请号：US12426004
申请日：2009-04-17
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L27/06
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
摘要翻译：半导体器件包括源极区，漏极区，栅极区和漂移区。漂移区域还包括有源漂移区域和无效浮动充电控制（FCC）区域。当电压施加到栅极区域时，有源漂移区域在源极区域和漏极区域之间导通电流。场地形成有源漂移区域以改善击穿电压的无活性FCC区域被垂直地堆叠在漂移区域中并且被有源漂移区域分离。垂直堆叠不活动的FCC区域可以降低导通电阻，同时保持更高的击穿电压。

5. 发明申请

US20080296636A1 Devices and integrated circuits including lateral floating capacitively coupled structures 审中-公开
标题翻译：器件和集成电路包括横向浮动电容耦合结构
公开(公告)号：US20080296636A1
公开(公告)日：2008-12-04
申请号：US12156670
申请日：2008-06-02
申请人： Mohamed N. Darwish , Richard A. Harris , Muhammed Ayman Shibib , Andrew J. Morrish , Robert Kuo-Chang Yang
发明人： Mohamed N. Darwish , Richard A. Harris , Muhammed Ayman Shibib , Andrew J. Morrish , Robert Kuo-Chang Yang
IPC分类号： H01L29/808 , H01L21/28 , H01L29/06
CPC分类号： H01L29/7835 , H01L21/765 , H01L21/823481 , H01L27/0266 , H01L27/0629 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/808
摘要： According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage. Further aspects of the invention relate to device integration, efficient fabrication of field shaping regions and device isolation features using the same mask for both, and improved device structures.
摘要翻译：根据本发明，可以通过在半导体器件的漂移区域内嵌入场成形区域来增加半导体器件击穿电压。可控电流路径在平面基板的顶表面上的两个器件端子之间延伸，并且可控电流路径包括漂移区域。每个场整形区域包括彼此电绝缘并且彼此电容耦合以形成分压第一和第二端子之间的电势的分压器的两个或更多个导电区域。一个或多个导电区域与任何外部电触点隔离。这种场成形区域可以在漂移区域的载流部分中提供增强的电场均匀性，从而增加器件击穿电压。本发明的其它方面涉及器件集成，场成形区域的有效制造和使用相同掩模的器件隔离特征和改进的器件结构。

6. 发明申请

US20120146140A1 HIGH-VOLTAGE SEMICONDUCTOR DEVICE WITH LATERAL SERIES CAPACITIVE STRUCTURE 有权
标题翻译：具有横向串联电容结构的高压半导体器件
公开(公告)号：US20120146140A1
公开(公告)日：2012-06-14
申请号：US13325712
申请日：2011-12-14
申请人： Mohamed N. Darwish , Robert Kuo-Chang Yang
发明人： Mohamed N. Darwish , Robert Kuo-Chang Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/407 , H01L29/66659
摘要： A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
摘要翻译：半导体器件包括半导体衬底，沿着半导体衬底的顶表面延伸的源极区域，沿着半导体衬底的顶表面延伸的漏极区域和设置在源极区域和半导体衬底之间的半导体衬底内的场整形区域漏区。通过场整形区域从源极区域延伸到漏极区域的半导体衬底的横截面包括绝缘区域。半导体器件还包括在源极区域和漏极区域之间设置在半导体衬底内的有源区域。有源区域在垂直于通过场整形区域从源极区域延伸到漏极区域的半导体衬底的横截面的方向上与场整形区域相邻设置。

7. 发明授权

US07514743B2 DMOS transistor with floating poly-filled trench for improved performance through 3-D field shaping 失效
标题翻译：具有浮动多晶填充沟槽的DMOS晶体管，用于通过3-D场成形改善性能
公开(公告)号：US07514743B2
公开(公告)日：2009-04-07
申请号：US11351644
申请日：2006-02-09
申请人： Robert Kuo-Chang Yang
发明人： Robert Kuo-Chang Yang
IPC分类号： H01L29/40
CPC分类号： H01L29/7802 , H01L21/823487 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7803 , H01L29/7813
摘要： One or more vertical DMOS transistors, such as trench FETS, are formed between opposing floating poly-filled trench portions. The opposing trench portions may include two parallel trenches, rectangular trenches, hexagonal trenches, octagonal trenches, circular trenches, or other shapes. The floating trench portions are capacitively coupled to assume a potential somewhere between the high drain voltage (below the trenches) and the body voltage (near the top of the trenches). The floating trench portions will have a potential below the drift region and deplete the drift region. The depletion regions caused by the opposing trench portions will merge under the gate with a sufficiently high drain voltage. The electric field lines in the drift region will be shaped to increase the breakdown voltage of the device.
摘要翻译：在相对的浮动多晶填充沟槽部分之间形成一个或多个垂直DMOS晶体管，例如沟槽FET。相对的沟槽部分可以包括两个平行的沟槽，矩形沟槽，六边形沟槽，八边形沟槽，圆形沟槽或其它形状。浮动沟槽部分电容耦合以在高漏极电压（沟槽下方）和体电压（靠近沟槽顶部）之间的某处存在电位。浮动沟槽部分将具有位于漂移区域下方的电位并耗尽漂移区域。由相对的沟槽部分引起的耗尽区域将在栅极下面以足够高的漏极电压合并。漂移区域中的电场线将被成形以增加器件的击穿电压。

8. 发明授权

US07535057B2 DMOS transistor with a poly-filled deep trench for improved performance 失效
标题翻译： DMOS晶体管具有多填充深沟槽，以提高性能
公开(公告)号：US07535057B2
公开(公告)日：2009-05-19
申请号：US11234519
申请日：2005-09-23
申请人： Robert Kuo-Chang Yang
发明人： Robert Kuo-Chang Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L29/0696 , H01L29/0878 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/7823
摘要： Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.
摘要翻译：浮动沟槽布置在单个DMOS晶体管或DMOS晶体管阵列的布局中，该阵列形成单个功率晶体管。沟槽在晶体管的外部或晶体管的行之间垂直于栅极宽度方向延伸。浮动沟槽处于漏极电压和衬底电压（通常为接地）之间的电位。相对沟槽的电位导致漂移区域中的耗尽区域的合并。这种合并形成场线，以增加晶体管的击穿电压并提供其它优点。该技术适用于横向和垂直DMOS晶体管。

9. 发明授权

US08704296B2 Trench junction field-effect transistor 有权
标题翻译：沟槽结场效应晶体管
公开(公告)号：US08704296B2
公开(公告)日：2014-04-22
申请号：US13408212
申请日：2012-02-29
申请人： Robert Kuo-Chang Yang
发明人： Robert Kuo-Chang Yang
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L29/1608 , H01L29/20 , H01L29/808
摘要： In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.
摘要翻译：在一般方面，半导体器件可以包括具有设置在结型场效应晶体管器件的第一沟槽内的第一沟槽部分的第一沟槽部分，以及设置在结型场效应晶体管器件的第二沟槽内的第二沟道部分，以及耦合到第一沟槽部分和第二沟槽部分的顶部。半导体器件可以包括设置在第一沟槽和第二沟槽之间的台面区域，并且包括由具有第一掺杂剂类型的衬底掺杂区域和具有第二掺杂剂类型的沟道掺杂剂区域之间的界面限定的单个PN结。

10. 发明授权

US08592906B2 High-voltage semiconductor device with lateral series capacitive structure 有权
标题翻译：具有横向串联电容结构的高压半导体器件
公开(公告)号：US08592906B2
公开(公告)日：2013-11-26
申请号：US13325712
申请日：2011-12-14
申请人： Mohamed N. Darwish , Robert Kuo-Chang Yang
发明人： Mohamed N. Darwish , Robert Kuo-Chang Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/407 , H01L29/66659
摘要： A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region.
摘要翻译：半导体器件包括半导体衬底，沿着半导体衬底的顶表面延伸的源极区域，沿着半导体衬底的顶表面延伸的漏极区域和设置在源极区域和半导体衬底之间的半导体衬底内的场整形区域漏区。通过场整形区域从源极区域延伸到漏极区域的半导体衬底的横截面包括绝缘区域。半导体器件还包括在源极区域和漏极区域之间设置在半导体衬底内的有源区域。有源区域在垂直于通过场整形区域从源极区域延伸到漏极区域的半导体衬底的横截面的方向上与场整形区域相邻设置。

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