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1. 发明授权

US07349288B1 Ultra high-speed Nor-type LSDL/Domino combined address decoder 失效
标题翻译：超高速Nor型LSDL / Domino组合地址解码器
公开(公告)号：US07349288B1
公开(公告)日：2008-03-25
申请号：US11538877
申请日：2006-10-05
申请人： Robert Kevin Montoye , Yutaka Nakamura
发明人： Robert Kevin Montoye , Yutaka Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
摘要翻译：超高速地址解码器使用Domino逻辑电路和LSDL逻辑电路的组合。 N个地址位转换为N个逻辑真地址位和N个互补地址位。部分地址解码器使用NOR逻辑结构中的N个逻辑真地址位和N个互补地址位来生成两个位组，因此在逻辑树中仅使用两个级联的NFETS。这些位组被划分以优化地址解码器中的并行位线的布局。

2. 发明申请

US20080084777A1 ULTRA HIGH-SPEED NOR-TYPE LSDL/DOMINO COMBINED ADDRESS DECODER 失效
标题翻译：超高速NOR型LSDL /多米诺组合地址解码器
公开(公告)号：US20080084777A1
公开(公告)日：2008-04-10
申请号：US11538877
申请日：2006-10-05
申请人： Robert Kevin Montoye , Yutaka Nakamura
发明人： Robert Kevin Montoye , Yutaka Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address hits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
摘要翻译：超高速地址解码器使用Domino逻辑电路和LSDL逻辑电路的组合。 N个地址匹配被转换为N个逻辑真地址位和N个互补地址位。部分地址解码器使用NOR逻辑结构中的N个逻辑真地址位和N个互补地址位来生成两个位组，因此在逻辑树中仅使用两个级联的NFETS。这些位组被划分以优化地址解码器中的并行位线的布局。

3. 发明授权

US08954350B2 Order supporting apparatus, control method for an order supporting apparatus, order supporting system, and computer readable storage medium 有权
标题翻译：订单支持设备，订单支持设备的控制方法，订单支持系统和计算机可读存储介质
公开(公告)号：US08954350B2
公开(公告)日：2015-02-10
申请号：US11944913
申请日：2007-11-26
申请人： Keiji Nagai , Yutaka Nakamura , Koji Dan , Masato Takahashi , Yuuki Inoue , Fujio Takahashi , Yoshiaki Murata
发明人： Keiji Nagai , Yutaka Nakamura , Koji Dan , Masato Takahashi , Yuuki Inoue , Fujio Takahashi , Yoshiaki Murata
IPC分类号： G06Q10/00 , G06Q20/00 , G06Q20/20 , G06Q10/08 , G06Q10/06 , G06Q30/06 , G06Q30/02 , G07G1/14
CPC分类号： G06Q10/00 , G06Q10/06 , G06Q10/08 , G06Q10/087 , G06Q10/0875 , G06Q20/20 , G06Q20/202 , G06Q20/203 , G06Q30/02 , G06Q30/06 , G07G1/14
摘要： An order supporting apparatus connected to a monitoring apparatus over a network, the monitoring apparatus determining a supply status of devices in the network and sends supply shortage information regarding at least one of the devices determined to have a supply shortage to the order supporting apparatus. In particular, the order supporting apparatus includes a device information storage part that stores device information describing whether each device is monitored as a monitoring target, and maintenance contract information of each device, and a determination part that determines, based on the device information, whether each device is subject to the maintenance contract when the order supporting apparatus receives the supply shortage information. Further, the determination part deselects, in the device information, a device as the monitoring target when the device is determined to have a supply shortage by the monitoring apparatus.
摘要翻译：一种通过网络连接到监视装置的订单支持装置，所述监视装置确定网络中的设备的供应状态，并且发送关于被确定为具有供应不足的订单支持设备的至少一个设备的供应不足信息。特别地，订单支持装置包括：设备信息存储部，其存储描述每个设备是否被监视作为监控对象的设备信息;以及每个设备的维护合同信息;以及确定部，其基于设备信息来确定是否当订单支持设备接收到供应不足信息时，每个设备都受到维护合同的约束。此外，当确定装置被确定为具有监视装置的供应不足时，确定部件在装置信息中取消选择作为监视对象的装置。

4. 发明申请

US20120287705A1 Spin-Torque Transfer Magneto-Resistive Memory Architecture 失效
标题翻译：自旋转移磁阻存储器架构
公开(公告)号：US20120287705A1
公开(公告)日：2012-11-15
申请号：US13558644
申请日：2012-07-26
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A method for operating a memory array device, includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLTE) of the device.
摘要翻译：一种用于操作存储器阵列器件的方法，包括在器件中启动写入0状态，其中启动写入0状态包括在器件的字线中引入第一电压; 以及在所述器件的第一位线（BLTE）中感应第二电压。

5. 发明授权

US08225518B2 Manual surveying instrument having collimation assisting device 有权
标题翻译：具有准直辅助装置的手动测量仪器
公开(公告)号：US08225518B2
公开(公告)日：2012-07-24
申请号：US13057785
申请日：2009-05-29
申请人： Satoshi Yanobe , Yutaka Nakamura
发明人： Satoshi Yanobe , Yutaka Nakamura
IPC分类号： G01C5/00
CPC分类号： G01C15/00
摘要： [Problem] To provide a manual surveying instrument that allows easily performing a collimating operation and allows performing a high precision measurement in a short time.[Solution Means] The manual surveying instrument includes a collimation assist device (70) having a collimation light transmitting system that emits a collimation light (R) along a collimation axis (O) toward a target installed at a measurement point, an area sensor (80) that obtains an image of a scene captured within a field of view of a collimating telescope (3), a display unit (48) that displays the image, a collimation light detecting unit (82) that detects the target as a result of receiving the collimation light reflected on the target by the area sensor, and an arithmetic control unit (46) that displays an area (94) being within a predetermined deviation from the collimation axis and where distance measurement is possible and a symbol indicating the target on the display unit as an animation image, judges that collimation has been completed when the target has been captured, by a manual operation of the collimating telescope, within the area where distance measurement is possible to perform a distance and angle measurement, and corrects an angle measurement value according to a deviation from the collimation axis of the target.
摘要翻译： [问题]提供一种能够容易地进行准直操作并允许在短时间内执行高精度测量的手动测量仪器。 [解决方案]手动测量仪器包括准直辅助装置（70），准直辅助装置（70）具有准直光传输系统，其沿着准直轴（O）向安装在测量点处的目标发射准直光（R），区域传感器 80），其获得在准直望远镜（3）的视野内拍摄的场景的图像，显示图像的显示单元（48）;作为结果的结果检测目标的准直光检测单元（82）接收由所述区域传感器反射在所述目标上的准直光;以及运算控制单元，其显示与所述准直轴在预定偏差内的区域（94），并且能够进行距离测量，以及指示所述目标的符号显示单元作为动画图像，通过准直望远镜的手动操作，在可能进行距离测量的区域内，判断已经捕获目标时的准直已经完成执行距离和角度测量，并根据与目标的准直轴的偏差来校正角度测量值。

6. 发明授权

US08005725B2 Order supporting system, order supporting method, and recording medium 有权
标题翻译：订单支持系统，订单支持方式和记录介质
公开(公告)号：US08005725B2
公开(公告)日：2011-08-23
申请号：US11798756
申请日：2007-05-16
申请人： Masato Takahashi , Keiji Nagai , Koji Dan , Yutaka Nakamura , Yuuki Inoue , Fujio Takahashi , Shogo Hyakutake , Yoshiaki Murata , Kenichi Takeda
发明人： Masato Takahashi , Keiji Nagai , Koji Dan , Yutaka Nakamura , Yuuki Inoue , Fujio Takahashi , Shogo Hyakutake , Yoshiaki Murata , Kenichi Takeda
IPC分类号： G06Q30/00 , G06Q10/00
CPC分类号： G03G15/55 , G03G15/5079 , G03G15/553 , G06Q10/087 , G06Q30/0601 , G06Q30/0633
摘要： An order supporting system includes a machine monitoring apparatus including an obtaining part for repetitively obtaining status data of plural supplies of plural machines connected to a network, a storing part for storing the status data obtained by the obtaining part, a detecting part for detecting change in the status of the supply by comparing the status data stored in the storing part and new status data that is newly obtained by the obtaining part, and a transmitting part for transmitting status data corresponding to the supply of the machine from which status change is detected by the detecting part, and an order supporting apparatus for receiving the status data transmitted from the transmitting part via the network and transmitting an electronic mail to a mail address associated to the machine corresponding to the transmitted status data in accordance with the received status data.
摘要翻译：订单支持系统包括：机器监视装置，包括：重复获取连接到网络的多个机器的多个供应的状态数据的获取部，用于存储由获取部获得的状态数据的存储部;检测部，通过比较存储在存储部分中的状态数据和由获取部分新获得的新状态数据来提供供应的状态，以及发送部分，用于发送对应于通过以下步骤检测到状态改变的机器供应的状态数据：检测部分和用于经由网络接收从发送部分发送的状态数据的订单支持装置，并且根据接收到的状态数据将电子邮件发送到与发送的状态数据相对应的与机器相关联的邮件地址。

7. 发明授权

US07668024B2 Hybrid static and dynamic sensing for memory arrays 有权
标题翻译：用于存储器阵列的混合静态和动态感测
公开(公告)号：US07668024B2
公开(公告)日：2010-02-23
申请号：US11929875
申请日：2007-10-30
申请人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： G11C7/06
CPC分类号： G11C7/18 , G11C7/06 , G11C11/413
摘要： A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.
摘要翻译：用于存储器的混合电路包括：偏斜静态逻辑门电路; 与静态逻辑门电路相结合的动态预放电装置，用于将静态逻辑门电路作为动态电路进行操作。

8. 发明授权

US07616510B2 Dynamic semiconductor storage device and method for operating same 失效
标题翻译：动态半导体存储装置及其操作方法
公开(公告)号：US07616510B2
公开(公告)日：2009-11-10
申请号：US11848401
申请日：2007-08-31
申请人： Yutaka Nakamura
发明人： Yutaka Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4099
摘要： The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge bit lines BLt and /BLt to a ground voltage GND, and reference word lines RWLo and RWLe and reference memory cells RMC are arranged, so that when a word line WL is activated, a potential difference is always generated between the bit lines BLt and /BLt. The sources of transistors N10 and N11 of an N-type sense amplifier NSAt are connected directly to a ground terminal GND, and the sources of transistors P2 and P3 of a P-type sense amplifier PSA are connected directly to a power source VDD. The gates of the transistors N10 and N11 are connected to the bit lines /BLt and BLt, and the drains are connected to the bit lines BLt and /BLt, respectively. Shift word lines SWL and shift memory cells SMC are arranged, so that the N sense amplifier NSAt can amplify the potential difference between the bit lines BLt and /BLt.
摘要翻译：本发明的目的是提供一种DRAM，其中可以增加读出放大器的操作速度。位线预充电电路PCt和PCb布置成将位线BLt和/ BLt预充电到地电压GND，并且布置参考字线RWLo和RWLe以及参考存储单元RMC，使得当字线WL被激活时，总是在位线BLt和/ BLt之间产生差异。 N型读出放大器NSAt的晶体管N10和N11的源极直接连接到接地端子GND，P型读出放大器PSA的晶体管P2和P3的源极直接连接到电源VDD。晶体管N10和N11的栅极连接到位线BLt和BLt，漏极分别连接到位线BLt和/ BLt。移位字线SWL和移位存储器单元SMC被布置，使得N个读出放大器NSAt可以放大位线BLt和/ BLt之间的电位差。

9. 发明授权

US07616447B2 IC card 失效
标题翻译： IC卡
公开(公告)号：US07616447B2
公开(公告)日：2009-11-10
申请号：US11629789
申请日：2005-06-17
申请人： Hiroyuki Yamada , Yoshiteru Mori , Kenji Nishimura , Yutaka Nakamura
发明人： Hiroyuki Yamada , Yoshiteru Mori , Kenji Nishimura , Yutaka Nakamura
IPC分类号： H05K1/14
CPC分类号： G06K19/07345 , G06K19/07732
摘要： An IC memory card (11) has a mode change switch (18) for switching operation modes of a semiconductor component in the vicinity of an end side opposite the external connection terminals (17a to 17i). A controller LSI (24) detects the status of the mode change switch (18) and switches operation modes according to the detected status.
摘要翻译： IC存储卡（11）具有用于切换与外部连接端子（17a至17i）相对的端侧附近的半导体部件的操作模式的模式切换开关（18）。控制器LSI（24）根据检测到的状态检测模式切换开关（18）的状态并切换动作模式。

10. 外观设计

USD588135S1 IC memory card 有权
公开(公告)号：USD588135S1
公开(公告)日：2009-03-10
申请号：US29325204
申请日：2008-09-26
申请人： Yutaka Nakamura
设计人： Yutaka Nakamura

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