专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07904870B2 Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering 有权
标题翻译：集成电路设计模型性能评估的方法和装置，采用基本的块矢量聚类和飞行矢量聚类
公开(公告)号：US07904870B2
公开(公告)日：2011-03-08
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

2. 发明授权

US08245084B2 Two-level representative workload phase detection 有权
标题翻译：两级代表性工作负载相位检测
公开(公告)号：US08245084B2
公开(公告)日：2012-08-14
申请号：US11972678
申请日：2008-01-11
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F11/00
CPC分类号： G06F11/3414 , G06F11/3476 , G06F2201/885
摘要： A subset of a workload, which includes a total set of dynamic instructions, is identified to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that most closely represents the execution of the entire workload using the particular dataset to use as a trace.
摘要翻译：工作负载的一个子集（其中包含一整套动态指令）被识别为跟踪。处理器单元硬件使用特定数据集实时执行整个工作负载。处理器单元硬件包括至少一个微处理器和至少一个高速缓存。监视工作负载的实时执行，以获取有关当使用特定数据集执行工作负载以形成实际性能信息时处理器单元硬件如何执行工作负载的信息。生成多个不同的工作负载子集。将处理器单元硬件的每个子集的执行与实际的性能信息进行比较。使用比较的结果来选择使用特定数据集作为跟踪最接近地表示整个工作负荷的执行的多个不同子集中的一个。

3. 发明申请

US20090182994A1 TWO-LEVEL REPRESENTATIVE WORKLOAD PHASE DETECTION METHOD, APPARATUS, AND COMPUTER USABLE PROGRAM CODE 有权
标题翻译：两级代表性工作负载相位检测方法，装置和计算机可用程序代码
公开(公告)号：US20090182994A1
公开(公告)日：2009-07-16
申请号：US11972678
申请日：2008-01-11
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/3414 , G06F11/3476 , G06F2201/885
摘要： A method, apparatus, and computer-usable program code in a computer system for identifying a subset of a workload, which includes a total set of dynamic instructions, to use as a trace. Processor unit hardware executes the entire workload in real-time using a particular dataset. The processor unit hardware includes at least one microprocessor and at least one cache. The real-time execution of the workload is monitored to obtain information about how the processor unit hardware executes the workload when the workload is executed using the particular dataset to form actual performance information. Multiple different subsets of the workload are generated. The execution of each one of the subsets by the processor unit hardware is compared with the actual performance information. A result of the comparison is used to select one of the plurality of different subsets that roost closely represents the execution of the entire workload using the particular dataset to use as a trace.
摘要翻译：一种计算机系统中的方法，装置和计算机可用的程序代码，用于识别工作负载的子集，其包括一组动态指令，用作跟踪。处理器单元硬件使用特定数据集实时执行整个工作负载。处理器单元硬件包括至少一个微处理器和至少一个高速缓存。监视工作负载的实时执行，以获取有关当使用特定数据集执行工作负载以形成实际性能信息时处理器单元硬件如何执行工作负载的信息。生成多个不同的工作负载子集。将处理器单元硬件的每个子集的执行与实际的性能信息进行比较。比较的结果被用于选择多个不同的子集中的一个，这些子集中使用特定的数据集作为跟踪来密切地表示整个工作负荷的执行。

4. 发明申请

US20080294881A1 METHOD AND APPARATUS FOR INSTRUCTION COMPLETION STALL IDENTIFICATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：信息处理系统中指示完成标识的方法和装置
公开(公告)号：US20080294881A1
公开(公告)日：2008-11-27
申请号：US11753005
申请日：2007-05-24
申请人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
发明人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.
摘要翻译：信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

5. 发明授权

US08832416B2 Method and apparatus for instruction completion stall identification in an information handling system 有权
标题翻译：信息处理系统中指令完成失速识别的方法和装置
公开(公告)号：US08832416B2
公开(公告)日：2014-09-09
申请号：US11753005
申请日：2007-05-24
申请人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
发明人： Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Alexander Erik Mericas , Mysore Sathyanarayana Srinivas
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.
摘要翻译：信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

6. 发明授权

US08234484B2 Quantifying completion stalls using instruction sampling 失效
标题翻译：使用指令采样量化完成档位
公开(公告)号：US08234484B2
公开(公告)日：2012-07-31
申请号：US12099944
申请日：2008-04-09
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3802 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F9/3885 , G06F11/3466 , G06F11/348 , G06F2201/86
摘要： A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are.
摘要翻译：公开了一种用于在具有分支预测的无序超标量处理器中收集关于完成停顿的度量的方法，计算机程序产品和数据处理系统。本发明的优选实施例有选择地对特定指令（或指令类别）进行采样。每个选定的指令在通过处理器数据路径时被标记（标记），用于由性能监视单元监视。标记指令的进度由性能监控单元进行监控，各种失速计数器由标记指令和指令组的进度触发。停顿计数器计数周期，以指示何时发生与特定指令相关的某些延迟以及延迟的严重程度。

7. 发明授权

US07617385B2 Method and apparatus for measuring pipeline stalls in a microprocessor 有权
标题翻译：用于测量微处理器中管道停顿的方法和装置
公开(公告)号：US07617385B2
公开(公告)日：2009-11-10
申请号：US11675112
申请日：2007-02-15
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F11/28
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F11/3423 , G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.
摘要翻译：一种计算机实现的方法，装置和计算机程序产品，用于监视指令流水线中的指令的执行。该过程识别一组完成执行的指令的停顿周期数。该过程检索对应于该组指令的确定性延迟模式。该过程将停顿周期数与确定性执行延迟模式进行比较。响应于确定指令组中的指令在前提指令完成之后完成确定性循环次数，该过程将该指令标识为依赖指令。

8. 发明申请

US20080201566A1 METHOD AND APPARATUS FOR MEASURING PIPELINE STALLS IN A MICROPROCESSOR 有权
标题翻译：用于测量微处理器中管道的方法和装置
公开(公告)号：US20080201566A1
公开(公告)日：2008-08-21
申请号：US11675112
申请日：2007-02-15
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F11/3423 , G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.
摘要翻译：一种计算机实现的方法，装置和计算机程序产品，用于监视指令流水线中的指令的执行。该过程识别一组完成执行的指令的停顿周期数。该过程检索对应于该组指令的确定性延迟模式。该过程将停顿周期数与确定性执行延迟模式进行比较。响应于确定指令组中的指令在前提指令完成之后完成确定性循环次数，该过程将该指令标识为依赖指令。

9. 发明授权

US10169187B2 Processor core having a saturating event counter for making performance measurements 有权
公开(公告)号：US10169187B2
公开(公告)日：2019-01-01
申请号：US12858497
申请日：2010-08-18
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F11/34
摘要： A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.

10. 发明申请

US20120046912A1 PROCESSOR CORE HAVING A SATURATING EVENT COUNTER FOR MAKING PERFORMANCE MEASUREMENTS 审中-公开
标题翻译：具有制作性能测量的饱和活动计数器的处理器芯
公开(公告)号：US20120046912A1
公开(公告)日：2012-02-23
申请号：US12858497
申请日：2010-08-18
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F15/00
CPC分类号： G06F11/348 , G06F2201/88
摘要： A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.
摘要翻译：包括饱和计数器的性能监视器提供事件频率的相对度量，而不需要最小轮询速率或周期性复位来避免或考虑计数器溢出。饱和计数器在检测到事件时增加，并且如果在预定时间段内未检测到事件，则递减计数器。检测周期可以是可编程的，并且可以通过实时时钟，处理器或指令周期来确定。可以选择多个事件类型用于检测和输入到单个计数器，或者可以为各种事件类型提供多个事件计数器。饱和计数器可以另外在所选择的操作模式中周期性地复位，并结合在计数器上执行的递减动作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式