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1. 发明授权

US6031992A Combining hardware and software to provide an improved microprocessor 失效
标题翻译：结合硬件和软件提供改进的微处理器
公开(公告)号：US6031992A
公开(公告)日：2000-02-29
申请号：US678541
申请日：1996-07-05
申请人： Robert F. Cmelik , David R. Ditzel , Edmund J. Kelly , Colin B. Hunter , Douglas A. Laird , Malcolm John Wing , Grzegorz B. Zyner
发明人： Robert F. Cmelik , David R. Ditzel , Edmund J. Kelly , Colin B. Hunter , Douglas A. Laird , Malcolm John Wing , Grzegorz B. Zyner
IPC分类号： G06F9/318 , G06F9/38 , G06F9/455 , G06F9/45
CPC分类号： G06F9/3812 , G06F9/3017 , G06F9/30174 , G06F9/45504
摘要： A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.
摘要翻译：一种用于主计算机的微处理器，被设计用于执行目标计算机的目标应用程序，所述目标计算机具有目标指令集，所述目标指令集包括代码变形软件的组合，以及被设计为执行主机指令集的指令的变形主机处理硬件，代码变形软件和变形主机处理硬件包括将一组目标指令转换为主机指令集的指令的装置，用于优化从发生条件时推测的目标应用程序翻译的主机指令集的指令的装置，在由微处理器在目标应用程序执行期间在一组目标指令的转换开始时存在的目标计算机的代码变形软件官方状态的控制下确定用于从目标计算机的状态更新目标计算机的状态的装置主机当一套主机指令时根据推测执行的装置，用于在执行主机指令集期间检测状况的失败的手段，用于当主机指令的集合根据不可执行的主机指令不能执行时从目标计算机的状态更新主机的状态的装置当一组主机指令根据推测不能执行时，这种推测和翻译一组新的主机指令的手段无需推测。

2. 发明授权

US08370785B2 Software controlled transistor body bias 有权
标题翻译：软件控制晶体管体偏置
公开(公告)号：US08370785B2
公开(公告)日：2013-02-05
申请号：US13168896
申请日：2011-06-24
申请人： David R. Ditzel , James B. Burr
发明人： David R. Ditzel , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.
摘要翻译：软件控制晶体管体偏置。访问目标频率。使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。晶体管的主体基于主体偏置值被偏置，其中特性被增强。

3. 发明申请

US20080141187A1 SOFTWARE CONTROLLED TRANSISTOR BODY BIAS 有权
标题翻译：软件控制的晶体管体偏置
公开(公告)号：US20080141187A1
公开(公告)日：2008-06-12
申请号：US12033832
申请日：2008-02-19
申请人： David R. Ditzel , James B. Burr
发明人： David R. Ditzel , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.
摘要翻译：软件控制晶体管体偏置。访问目标频率。使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。晶体管的主体基于主体偏置值被偏置，其中特性被增强。

4. 发明授权

US09213523B2 Double rounded combined floating-point multiply and add 有权
标题翻译：双圆形组合浮点乘法和加法
公开(公告)号：US09213523B2
公开(公告)日：2015-12-15
申请号：US13539198
申请日：2012-06-29
申请人： Sridhar Samudrala , Grigorios Magklis , Marc Lupon , David R. Ditzel
发明人： Sridhar Samudrala , Grigorios Magklis , Marc Lupon , David R. Ditzel
IPC分类号： G06F7/38 , G06F7/483 , G06F7/544
CPC分类号： G06F7/4876 , G06F7/483 , G06F7/485 , G06F7/4991 , G06F7/49915 , G06F7/5443 , G06F2207/4802
摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.
摘要翻译：公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数，基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。分别使用溢出检测选择最终结果。

5. 发明授权

US07579221B1 Conversion of an SOI design layout to a bulk design layout 有权
标题翻译：将SOI设计布局转换为批量设计布局
公开(公告)号：US07579221B1
公开(公告)日：2009-08-25
申请号：US11393555
申请日：2006-03-29
申请人： David R. Ditzel , James B. Burr , Robert P. Masleid
发明人： David R. Ditzel , James B. Burr , Robert P. Masleid
IPC分类号： H01L21/00 , H01L21/84 , H01L21/20 , H01L21/36
CPC分类号： H01L27/0207 , H01L21/823878 , H01L21/84 , H01L27/0617 , H01L27/1203
摘要： An SOI design layout is converted to a bulk design layout. According to a method of converting a first semiconductor design layout based on an Silicon-on-Insulator (SOI) process to a second semiconductor design layout based on a bulk process, an insulator layer of the SOI process beneath active devices in the first semiconductor design layout is removed. A conductive sub-surface structure for routing voltage is added to the first semiconductor design layout. Further, the active devices from the SOI process are converted to the bulk process to form the second semiconductor design layout without requiring a relayout of the first semiconductor design layout on a semiconductor surface. The bulk design layout is utilized to fabricate a semiconductor device having a plurality of active devices.
摘要翻译： SOI设计布局被转换为散装设计布局。根据基于体积工艺将基于绝缘体上硅（SOI）工艺的第一半导体设计布局转换为第二半导体设计布局的方法，在第一半导体设计中的有源器件下方的SOI工艺的绝缘体层布局被删除。用于路由电压的导电子表面结构被添加到第一半导体设计布局。此外，来自SOI工艺的有源器件被转换为本体处理以形成第二半导体设计布局，而不需要在半导体表面上重新布置第一半导体设计布局。本体设计布局用于制造具有多个有源器件的半导体器件。

6. 发明授权

US07334198B2 Software controlled transistor body bias 有权
标题翻译：软件控制晶体管体偏置
公开(公告)号：US07334198B2
公开(公告)日：2008-02-19
申请号：US10334638
申请日：2002-12-31
申请人： David R. Ditzel , James B. Burr
发明人： David R. Ditzel , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Software controlled body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is optimized.
摘要翻译：软件控制体偏。访问目标频率。使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。晶体管的主体基于身体偏置值被偏置，其中特性被优化。

7. 发明授权

US4853889A Arrangement and method for speeding the operation of branch instructions 失效
标题翻译：分支指令运行加快的安排和方法
公开(公告)号：US4853889A
公开(公告)日：1989-08-01
申请号：US48210
申请日：1987-05-11
申请人： David R. Ditzel , Hubert R. McLellan, Jr.
发明人： David R. Ditzel , Hubert R. McLellan, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3804
摘要： Arrangement and method for avoiding the processing time associated with executing branch instructions in a computer. An instruction fetch unit appends a next instruction address field to each instruction it passes it via an instruction cache to an instruction execution unit. The fetch unit decodes the present instruction being read and the next sequential instruction in main memory. If neither instruction is a branch instruction, the next address field is set to the address of the next sequential instruction. If the present instruction is a branch, the next instruction address field is set to the branch address contained in the present instruction. If neither of these cases are true and the next sequential instruction from main memory is a branch, the next instruction address field is set to the branch address of this instruction. The execution unit uses the next instruction address to access instructions from the instruction cache. Thus, execution of branch instructions by the execution unit are avoided.
摘要翻译：用于避免与计算机中执行分支指令相关联的处理时间的布置和方法。指令提取单元将下一个指令地址字段附加到其通过指令高速缓存的指令到指令执行单元。提取单元对正在读取的当前指令和主存储器中的下一个顺序指令进行解码。如果两条指令都不是分支指令，则下一个地址字段被设置为下一个顺序指令的地址。如果当前指令是分支，则将下一个指令地址字段设置为当前指令中包含的分支地址。如果这两种情况都不为真，并且主存储器的下一个顺序指令是分支，则下一个指令地址字段被设置为该指令的分支地址。执行单元使用下一个指令地址来访问来自指令高速缓存的指令。因此，避免了由执行单元执行分支指令。

8. 发明申请

US20110258590A1 SOFTWARE CONTROLLED TRANSISTOR BODY BIAS 有权
标题翻译：软件控制晶体管体偏置
公开(公告)号：US20110258590A1
公开(公告)日：2011-10-20
申请号：US13168896
申请日：2011-06-24
申请人： David R. Ditzel , James B. Burr
发明人： David R. Ditzel , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.
摘要翻译：软件控制晶体管体偏置。访问目标频率。使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。晶体管的主体基于主体偏置值被偏置，其中特性被增强。

9. 发明授权

US5043870A Computer with automatic mapping of memory contents into machine registers during program execution 失效
标题翻译：计算机在程序执行期间将内存内容自动映射到机器寄存器中
公开(公告)号：US5043870A
公开(公告)日：1991-08-27
申请号：US368089
申请日：1989-07-19
申请人： David R. Ditzel , Hubert R. McLellan, Jr.
发明人： David R. Ditzel , Hubert R. McLellan, Jr.
IPC分类号： G06F9/34 , G06F9/38 , G06F9/42
CPC分类号： G06F9/382 , G06F9/34 , G06F9/3824 , G06F9/4426 , G06F2212/451
摘要： A computer system arranged for faster processing operations by providing a stack cache in internal register memory. A full stack is provided in main memory. The stack cache provides a cache representation of part of the main memory stack. Stack relative addresses contained in procedure instructions are converted to absolute main memory stack addresses. A subset of the absolute main memory stack address is used to directly address the stack cache when a "hit" is detected. Otherwise, the main memory stack is addressed. The stack cache is implemented as a set of contiguously addressable registers. Two stack pointers are used to implement allocation space in the stack as a circulating buffer. Cache hits are detected by comparing the absolute stack address to the contents of the two circular buffer pointers. Space for a procedure is allocated upon entering a procedure. The amount of space to allocate is stored in the first instruction. Space is deallocated when a procedure is terminated. The deallocation space is stored in the first instruction executed after procedure termination.
摘要翻译：一种计算机系统，其通过在内部寄存器存储器中提供堆栈高速缓存来设置用于更快的处理操作。主存储器中提供了一个完整的堆栈。堆栈缓存提供主存储器堆栈的一部分的高速缓存表示。过程指令中包含的堆栈相对地址将转换为绝对主存储器堆栈地址。当检测到“命中”时，绝对主存储器堆栈地址的子集用于直接寻址堆栈高速缓存。否则，主存储器堆栈被寻址。堆栈缓存被实现为一组可连续寻址的寄存器。两个堆栈指针用于在栈中实现分配空间作为循环缓冲区。通过将绝对堆栈地址与两个循环缓冲区指针的内容进行比较来检测缓存命中。进入程序时分配空格。要分配的空间量存储在第一条指令中。当程序终止时，空间被释放。解除分配空间存储在程序终止后执行的第一条指令中。

10. 发明申请

US20140033160A1 SOFTWARE CONTROLLED TRANSISTOR BODY BIAS 有权
标题翻译：软件控制晶体管体偏置
公开(公告)号：US20140033160A1
公开(公告)日：2014-01-30
申请号：US13741246
申请日：2013-01-14
申请人： David R. Ditzel , James B. Burr
发明人： David R. Ditzel , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.
摘要翻译：软件控制晶体管体偏置。访问目标频率。使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。晶体管的主体基于主体偏置值被偏置，其中特性被增强。

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