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1. 发明授权

US5966546A Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node 失效
标题翻译：用于在网络节点中执行TX原始小区状态报告频率和中断频率减轻的方法和装置
公开(公告)号：US5966546A
公开(公告)日：1999-10-12
申请号：US707895
申请日：1996-09-12
申请人： Robert E. Thomas , Theodore L. Ross , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung , Koichi Tanaka , Shinichi Mizuguchi
发明人： Robert E. Thomas , Theodore L. Ross , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung , Koichi Tanaka , Shinichi Mizuguchi
IPC分类号： G06F13/38 , H04L12/56 , G06F13/14
CPC分类号： G06F13/387 , H04L2012/5616 , H04L2012/5658
摘要： A mechanism by which interrupt frequency mitigation is combined with transmit raw cell status report frequency mitigation is presented. A tx raw cell status report is allowed to occur for only every N raw cell tx slots consumed. When the rate of interrupt requests is mitigated in accordance with holdoff parameters including a holdoff event count corresponding to X interrupt events and a holdoff time interval, and the raw cell status report counts as an interrupt event, an interrupt request is generated for an enabled interrupt if N*X events has occurred or the holdoff time interval has elapsed.
摘要翻译：提出了一种将中断频率缓解与发送原始小区状态报告频率缓解相结合的机制。只有消耗的每个N个原始单元格tx槽才允许出现tx原始单元状态报告。当中断请求的速率根据包括对应于X中断事件的缓存事件计数和释放时间间隔的保留参数进行缓解，并且原始单元状态报告计数为中断事件时，会为使能中断产生中断请求如果N * X事件已经发生或释放时间间隔已经过去。

2. 发明授权

US06466997B1 Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node 有权
标题翻译：用于在网络节点中执行TX原始小区状态报告频率和中断频率减轻的方法和装置
公开(公告)号：US06466997B1
公开(公告)日：2002-10-15
申请号：US09332836
申请日：1999-06-14
申请人： Theodore L. Ross , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung , Koichi Tanaka , Shinichi Mizuguchi , Robert E. Thomas
发明人： Theodore L. Ross , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung , Koichi Tanaka , Shinichi Mizuguchi , Robert E. Thomas
IPC分类号： G06F500
CPC分类号： G06F13/387 , H04L2012/5616 , H04L2012/5658
摘要： A method and system for requesting an interrupt from a host system to service an adapter connected to the host system and a data interface. Data packets, including one or more data cells, are transferred between the data interface and the host system. The host system includes a host memory that includes a plurality of memory slots to store data packets transferred between the data interface and the host system. It is determined when a transfer of data has resulted in an occurrence of an interrupt event. An interrupt event occurs when the transfer of data includes a transfer of a data cell between the data interface and the host system and the data cell is defined to be an end of a data packet. In response to the occurrence of an interrupt event, it is determined whether to generate an interrupt request to the host system. This step of determining includes determining whether a predetermined interval of time has elapsed since the host system last processed an interrupt request or determining whether a predetermined number of interrupt events have occurred since the host system last processed an interrupt request. If the predetermined interval of time has elapsed or the predetermined number of events has occurred, respectively, the interrupt request from the adapter to the host system is generated.
摘要翻译：一种用于从主机系统请求中断来服务连接到主机系统的适配器和数据接口的方法和系统。包括一个或多个数据单元的数据包在数据接口和主机系统之间传输。主机系统包括主机存储器，其包括多个存储器插槽以存储在数据接口和主机系统之间传送的数据包。确定何时传输数据导致发生中断事件。当数据传输包括在数据接口和主机系统之间的数据信元的传送并且数据信元被定义为数据包的结尾时，发生中断事件。响应于中断事件的发生，确定是否向主机系统生成中断请求。该确定步骤包括确定从主机系统最后一次处理中断请求以来是否已经过去了预定的时间间隔，或者确定从主机系统最后一次处理中断请求以来是否发生了预定数量的中断事件。如果预定的时间间隔已经过去或预定的事件数量分别发生，则从适配器向主机系统产生中断请求。

3. 发明授权

US5867480A Method and apparatus for controlling congestion in a network node 失效
标题翻译：控制网络节点拥塞的方法和装置
公开(公告)号：US5867480A
公开(公告)日：1999-02-02
申请号：US712683
申请日：1996-09-12
申请人： Robert E. Thomas , Koichi Tanaka , Peter J. Roman , Wing Cheung , Shinichi Mizuguchi
发明人： Robert E. Thomas , Koichi Tanaka , Peter J. Roman , Wing Cheung , Shinichi Mizuguchi
IPC分类号： H04L12/56 , G01R31/08 , G06F11/00 , G08C15/00
CPC分类号： H04L12/5602 , H04L2012/5635 , H04L2012/5637 , H04L2012/5679
摘要： In a network node having a host system coupled to a network by an adapter, VC-specific congestion is detected and reported to the host system. The host memory includes rx slots or buffers, each corresponding to one of one or more supported slot types. Per-VC slots consumed counters are maintained to count slot consumption for each active VC. Free buffer FIFOs are maintained for each of the one or more slot types, which have a predetermined congestion threshold associated therewith. Entries in each free buffer FIFO correspond to an rx slot posted by the host system. When a new rx slot or buffer in host memory is to be allocated to an incoming cell received on a given VC, the slots consumed counter is compared to the predetermined congestion threshold. If they are equal, the VC is at threshold level and the incoming cell is discarded and a report is sent to the host system. If the slots consumed counter is below threshold, a new rx slot is allocated for the reception of the data and the slots consumed counter is incremented. If the VC is credit-based flow control enabled and the slots consumed counter is below threshold, a credit is returned. If the VC is credit-based flow control enabled and the slots consumed counter is greater than or equal to the threshold, the credit return is deferred until the counter falls below threshold.
摘要翻译：在具有通过适配器耦合到网络的主机系统的网络节点中，检测到VC特定的拥塞并将其报告给主机系统。主机存储器包括rx时隙或缓冲器，每个对应于一个或多个支持的时隙类型之一。维护每个VC槽消耗的计数器以计算每个活动VC的时隙消耗。对于具有与其相关联的预定拥塞阈值的一个或多个时隙类型中的每一个，维持空闲缓冲器FIFO。每个空闲缓冲区FIFO中的条目对应于由主机系统发布的rx时隙。当将主机存储器中的新的rx时隙或缓冲区分配给在给定VC上接收到的传入小区时，将这些时隙消耗的计数器与预定拥塞阈值进行比较。如果它们相等，则VC处于阈值级别，并且传入的信元被丢弃并且报告被发送到主机系统。如果消耗的时隙计数器低于阈值，则为数据的接收分配一个新的rx时隙，并增加消耗的时隙计数器。如果VC是启用了基于信用的流量控制，并且消耗的消费计数器低于阈值，则返回信用。如果VC是启用了基于信用的流量控制，并且消费的时隙计数器大于或等于该阈值，那么信用回报被推迟到计数器低于阈值。

4. 发明授权

US6115775A Method and apparatus for performing interrupt frequency mitigation in a network node 失效
标题翻译：用于在网络节点中执行中断频率减轻的方法和装置
公开(公告)号：US6115775A
公开(公告)日：2000-09-05
申请号：US712688
申请日：1996-09-12
申请人： Theodore L. Ross , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung , Koichi Tanaka , Shinichi Mizuguchi
发明人： Theodore L. Ross , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung , Koichi Tanaka , Shinichi Mizuguchi
IPC分类号： G06F13/12 , H04L12/56 , G06F13/24
CPC分类号： H04L47/562 , G06F13/128 , H04L12/5693 , H04L47/52 , H04L47/6215 , H04L49/90 , H04L49/901 , H04L49/9063 , H04L49/9094
摘要： A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.
摘要翻译：提供了基于时间和基于事件的中断频率缓解方案。缓存事件计数器被编程为对与多个中断相对应的缓存事件计数进行计数。缓存定时器被编程为在发生对主机系统的中断请求的产生之前代表代表经过的时间段的中断间隔。当与来自主机系统或来自主机系统的数据传送相关联的数据传输请求被服务并且导致发生中断事件时，修正事件计数器被修改为1。如果暂停事件计数器或中断定时器已经到期并且中断被使能，则会产生对主机系统的中断请求。响应于这种中断请求生成，处理中断并且缓存事件计数器和保持定时器重新触发。

5. 发明授权

US5822612A Apparatus and method for managing schedule table pointers 失效
标题翻译：用于管理计划表指针的装置和方法
公开(公告)号：US5822612A
公开(公告)日：1998-10-13
申请号：US713047
申请日：1996-09-12
申请人： Robert E. Thomas , Peter J. Roman , Koichi Tanaka , Wing Cheung
发明人： Robert E. Thomas , Peter J. Roman , Koichi Tanaka , Wing Cheung
IPC分类号： H04L12/56 , H04Q11/04 , G06F13/00 , G06F13/28
CPC分类号： H04Q11/0478 , H04L2012/5658 , H04L2012/5679 , H04L2012/5681
摘要： An apparatus and method for scheduling data transfers between a host and adapter. A schedule table data structure resides in a memory on the adapter. Each location in the schedule table represents a point in time at which data is to be transmitted from the adapter. A current time counter advances at the rate at which data is to be transmitted from the node. A pointer points to successive locations in the schedule table, and advances through the schedule table at a rate faster than the current time counter advances so that the value stored in the pointer represents a point in time which is ahead of the point in time currently represented by the value output from the current time counter. A request for a data transfer between the host and adapter is generated when a valid entry exists at the location pointed to by the pointer. The value of the pointer at the time the request is generated is stored as the last valid time. When a new entry is to be stored in the schedule table, it is stored at a location in the schedule table immediately after the location corresponding to the last valid time, and the pointer is reset to point to the location immediately after the location corresponding to the last valid time.
摘要翻译：一种用于调度主机和适配器之间的数据传输的装置和方法。调度表数据结构驻留在适配器上的存储器中。调度表中的每个位置表示要从适配器发送数据的时间点。当前时间计数器以从节点发送数据的速率前进。指针指向调度表中的连续位置，并且以比当前时间计数器更快的速率前进到调度表，使得存储在指针中的值表示在当前表示的时间点之前的时间点由当前时间计数器输出的值。当指针所指向的位置存在有效条目时，会生成主机和适配器之间的数据传输请求。生成请求时指针的值存储为最后一个有效时间。当新的条目要存储在调度表中时，它被紧紧地存储在与最后有效时间相对应的位置之后的调度表中的一个位置处，并且指针被重新设置为指向紧邻在对应于最后一个有效时间。

6. 发明授权

US5999980A Apparatus and method for setting a congestion indicate bit in an backwards RM cell on an ATM network 失效
标题翻译：用于设置拥塞的装置和方法指示ATM网络上的后向RM小区中的比特
公开(公告)号：US5999980A
公开(公告)日：1999-12-07
申请号：US712717
申请日：1996-09-12
申请人： Koichi Tanaka , Peter J. Roman , Kohei Abe , Shinichi Mizuguchi
发明人： Koichi Tanaka , Peter J. Roman , Kohei Abe , Shinichi Mizuguchi
IPC分类号： H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5635
摘要： An apparatus and method for generating a congestion indication bit to be written to the CI field of a backwards RM ATM cell to be transmitted by a network interface utilizes a slot.sub.-- type congestion signal for indicating that the number of slots available for receiving cells is below a threshold limit, and a CI.sub.-- VC signal for indicating that the buffer space consumed by cells received on a particular VC has passed a threshold value. The CI bit in a backward RM cell for the VC when either the slot.sub.-- type congestion signal is set or the CI.sub.-- VC bit is set or the EFCI bit was set in the last data cell received by the network interface or the CI bit was set in the last forward RM cell transmitted by the network interface.
摘要翻译：用于生成要写入将由网络接口发送的后向RM ATM信元的CI字段的拥塞指示位的装置和方法利用时隙型拥塞信号，用于指示可用于接收小区的时隙数目在下面阈值限制和用于指示在特定VC上接收的小区消耗的缓冲器空间已经通过阈值的CI-VC信号。当设置时隙型拥塞信号或设置CI-VC位或者由网络接口或CI位接收到的最后一个数据单元中设置EFCI位时，VC的反向RM单元中的CI位位于设置在由网络接口发送的最后一个前向RM小区中。

7. 发明授权

US6067563A Method and apparatus for avoiding control reads in a network node 有权
标题翻译：用于避免网络节点中的控制读取的方法和装置
公开(公告)号：US6067563A
公开(公告)日：2000-05-23
申请号：US306588
申请日：1999-05-06
申请人： Robert E. Thomas , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung
IPC分类号： G06F11/30 , H04L12/56 , H04L29/06 , H04Q11/04 , G06F13/00
CPC分类号： H04L47/522 , G06F11/3006 , G06F11/3027 , G06F11/3055 , G06F11/3096 , H04L29/06 , H04L47/521 , H04L49/90 , H04L49/901 , H04L49/9036 , H04Q11/0478 , H04L2012/5616 , H04L2012/5635 , H04L2012/5658 , H04L2012/5679 , H04L2012/5681
摘要： A mechanism for avoiding an initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller to move data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.
摘要翻译：提出了一种用于避免在系统总线上启动控制读取事务的机制，该系统总线耦合具有主机存储器的主机系统和连接到外围单元的接口，因为数据在主机系统和外围设备之间移动。将与主机存储器中的数据存储器部分相关联的控制信息写入存储输出数据和数据存储器部分的数据存储器部分的接口以接收输入数据。该接口包括控制器，用于通过首先获得相关联的数据部分的控制信息来在主机存储器和接口之间移动数据。该接口通过系统总线写入与接口和主机存储器之间的数据移动相关联的状态报告。因此，该机制使得能够在没有异常条件的情况下通过系统进行数据传输而不启动控制读取。

8. 发明授权

US5970229A Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory 失效
标题翻译：用于执行从主机存储器到发送缓冲存储器的数据DMA传输的预先调度的装置和方法
公开(公告)号：US5970229A
公开(公告)日：1999-10-19
申请号：US707896
申请日：1996-09-12
申请人： Robert E. Thomas , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Peter J. Roman , Wing Cheung
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/387
摘要： An apparatus and method for transferring data from a source memory (e.g. a host memory) to a peripheral interface via a bus utilizes a transmit buffer memory coupled to the peripheral interface, and a current time counter advancing at the rate at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table data structure stores entries in some or all of its locations, where each location corresponds to a point in time at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table pointer is used for pointing to successive locations in the schedule table. The schedule table pointer advances at a rate faster than the current time counter advances so that the schedule table pointer represents a point in time which is ahead of the point in time currently output by the current time counter. A data transfer is initiated from the source memory to the transmit buffer memory via the bus when a valid entry is stored at the location in the schedule table pointed to by the schedule table pointer. The data is then transferred out of the transmit buffer memory to the peripheral interface when the current time counter reaches the value representing at least the same point in time that was represented by the schedule table pointer when the data transfer was initiated. Data transfers from the transmit buffer memory are thereby synchronized in time with their corresponding entries in the schedule table.
摘要翻译：用于经由总线将数据从源存储器（例如，主机存储器）传送到外围接口的装置和方法利用耦合到外围接口的发送缓冲存储器和以数据的速率前进的当前时间计数器从发送缓冲存储器传送到外设接口。调度表数据结构存储其部分或全部位置中的条目，其中每个位置对应于将数据从发送缓冲存储器传送到外围接口的时间点。调度表指针用于指向调度表中的连续位置。调度表指针以比当前时间计数器更快的速率前进，使得调度表指针表示在当前时间计数器当前输出的时间点之前的时间点。当有效条目存储在调度表指针指向的调度表中的位置时，通过总线从源存储器发送到发送缓冲存储器的数据传输。然后，当当前时间计数器达到表示数据传输启动时由调度表指针表示的至少相同的时间点的值时，将数据传送到发送缓冲存储器中的外设接口。因此，从发送缓冲存储器的数据传输在时间上与其在调度表中的相应条目同步。

9. 发明授权

US5941952A Apparatus and method for transferring data from a transmit buffer memory at a particular rate 失效
标题翻译：用于以特定速率从发送缓冲存储器传送数据的装置和方法
公开(公告)号：US5941952A
公开(公告)日：1999-08-24
申请号：US712687
申请日：1996-09-12
申请人： Robert E. Thomas , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Peter J. Roman , Wing Cheung
IPC分类号： H04L12/56 , H04Q11/04 , G06F13/38 , G06F15/17
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5635 , H04L2012/5658 , H04L2012/5664 , H04L2012/5667 , H04L2012/5679 , H04L2012/5681
摘要： An apparatus and method for transferring data from a source memory to a transmit buffer memory and then from the transmit buffer memory at a particular rate. A current time counter advances at the rate at which data is to be transmitted from the transmit buffer memory to the interface. A schedule memory stores entries, each valid entry being associated with data that is to be transmitted from the transmit buffer memory to the interface. A timestamp is associated with each valid entry in the schedule memory. Circuitry is then operative on each valid entry read from the schedule table to generate a request for a data transfer between the source memory and the transmit buffer memory; perform a data transfer from the source memory to the transmit buffer memory in response to the request; and transfer the data from the transmit buffer memory when the current time circuitry output reaches a value representing at least the same point in time that is represented by the timestamp associated with the entry for which the request was generated.
摘要翻译：一种用于将数据从源存储器传送到发送缓冲存储器然后以特定速率从发送缓冲存储器传送的装置和方法。当前时间计数器以数据从发送缓冲存储器发送到接口的速率前进。调度存储器存储条目，每个有效条目与要从发送缓冲存储器发送到接口的数据相关联。时间戳与调度存储器中的每个有效条目相关联。然后对从调度表读取的每个有效条目进行电路以产生对源存储器和发送缓冲存储器之间的数据传输的请求; 响应于该请求，执行从源存储器到发送缓冲存储器的数据传输; 并且当当前时间电路输出达到表示与由生成请求的条目相关联的时间戳表示的至少相同的时间点的值时，传送来自发送缓冲存储器的数据。

10. 发明授权

US5995995A Apparatus and method for scheduling virtual circuit data for DMA from a host memory to a transmit buffer memory 失效
标题翻译：用于将DMA的虚拟电路数据从主机存储器调度到发送缓冲存储器的装置和方法
公开(公告)号：US5995995A
公开(公告)日：1999-11-30
申请号：US712698
申请日：1996-09-12
申请人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Anna Charny , Wing Cheung
发明人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Anna Charny , Wing Cheung
IPC分类号： H04L12/56 , H04Q11/04 , G06F9/00
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5651 , H04L2012/5679
摘要： A method of scheduling the transmission of cells from a network node involves storing entries in a schedule table at predetermined locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head, rather than the tail, of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted. The VC is therefore the first VC transmitted from the list of VCs.
摘要翻译：调度来自网络节点的小区的传输的方法包括在预定位置处存储调度表中的条目，其中每个位置表示要发送小区的时间点。表中的每个条目包含指向在与表中的条目的位置相对应的时间被调度用于传输的小区的虚拟电路的列表的指针。当VC具有要在特定时间发送的小区时，VC排队到位于表中对应于表的时间的指针指向的VC列表的头部而不是尾部，传输单元。因此，VC是从VC列表中发送的第一个VC。

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