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1. 发明授权

US07120813B2 Method and apparatus for clock synthesis using universal serial bus downstream received signals 有权
标题翻译：使用通用串行总线下行接收信号的时钟合成方法和装置
公开(公告)号：US07120813B2
公开(公告)日：2006-10-10
申请号：US10352749
申请日：2003-01-28
申请人： Robert Antoine Leydier , Christophe Alain Pomet
发明人： Robert Antoine Leydier , Christophe Alain Pomet
IPC分类号： H04L7/04 , G06F13/14
CPC分类号： G06F1/04
摘要： In one form of the invention, a method for generating a local clock signal responsive to signals on a Universal Serial Bus (“USB”) includes generating a frequency-bearing clock signal by a free running oscillator on an integrated circuitry chip of a device coupled to the USB. The oscillator runs at a frequency that is substantially stable but initially known with substantial inaccuracy. A single ended bit-serial signal is extracted from received signals sent by a USB host or hub and timing signals are responsively asserted. A bit pattern is detected in the single ended bit-serial signal and intervals are measured during which the timing signals are asserted. The period P of the local clock signal is adjusted responsive to one of the measured intervals. In one variant, the initial inaccuracy is at least partly because the oscillator consists solely of circuitry on the chip.
摘要翻译：在本发明的一种形式中，响应于通用串行总线（“USB”）上的信号产生本地时钟信号的方法包括通过耦合的器件的集成电路芯片上的自由振荡器产生频率承载时钟信号到USB。振荡器以基本稳定的频率运行，但是最初以实质的不精确性已知。从USB主机或集线器发送的接收信号中提取单端比特串行信号，响应地确定定时信号。在单端比特串行信号中检测到位模式，并且在定时信号被断言期间测量间隔。本地时钟信号的周期P响应于测量的间隔之一来调整。在一个变型中，初始不准确性至少部分是因为振荡器仅由芯片上的电路组成。

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