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1. 发明授权

US07273806B2 Forming of high aspect ratio conductive structure using injection molded solder 有权
标题翻译：使用注塑焊料形成高纵横比导电结构
公开(公告)号：US07273806B2
公开(公告)日：2007-09-25
申请号：US10905013
申请日：2004-12-09
申请人： Robert A. Groves , Peter A. Gruber , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： Robert A. Groves , Peter A. Gruber , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L21/44
CPC分类号： H05K3/3468 , G01R1/07314 , G01R3/00 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L2224/13099 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01018 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/19041 , H01L2924/19042 , H05K3/325 , H05K2201/09745 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/128 , H05K2203/162 , H05K2203/167 , H01L2224/0401
摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
摘要翻译：公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。导电结构包括通过注射成型的焊料形成的高纵横比结构。本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。此外，该方法可以向后兼容并可定制。

2. 发明授权

US06534863B2 Common ball-limiting metallurgy for I/O sites 有权
公开(公告)号：US06534863B2
公开(公告)日：2003-03-18
申请号：US09781121
申请日：2001-02-09
申请人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
发明人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/16 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00015 , H01L2924/00012
摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

3. 发明授权

US06798029B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06798029B2
公开(公告)日：2004-09-28
申请号：US10434999
申请日：2003-05-09
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2982
CPC分类号： H01H59/0009 , H01H2059/0018 , H01H2059/0072
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

4. 发明授权

US07053460B2 Multi-level RF passive device 有权
公开(公告)号：US07053460B2
公开(公告)日：2006-05-30
申请号：US10026146
申请日：2001-12-21
申请人： Richard P. Volant , Seshadri Subbanna , Robert A. Groves , John C. Malinowski , Kenneth J. Stein , Kevin S. Petrarca
发明人： Richard P. Volant , Seshadri Subbanna , Robert A. Groves , John C. Malinowski , Kenneth J. Stein , Kevin S. Petrarca
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L23/66 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

5. 发明授权

US06635506B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06635506B2
公开(公告)日：2003-10-21
申请号：US10014660
申请日：2001-11-07
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2100
CPC分类号： B81C1/00246 , B81B2201/016 , B81B2201/018 , B81B2203/0127 , B81B2207/07 , B81C1/00611 , B81C2201/0122 , B81C2203/0735 , H01G5/40 , H01H59/0009
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

6. 发明授权

US06701779B2 Perpendicular torsion micro-electromechanical switch 失效
标题翻译：垂直扭转微机电开关
公开(公告)号：US06701779B2
公开(公告)日：2004-03-09
申请号：US10104972
申请日：2002-03-21
申请人： Richard P. Volant , Robert A. Groves , Kevin S. Petrarca , David M. Rockwell , Kenneth J. Stein
发明人： Richard P. Volant , Robert A. Groves , Kevin S. Petrarca , David M. Rockwell , Kenneth J. Stein
IPC分类号： G01P1500
CPC分类号： H01H59/0009 , B81B3/0021 , B81B2201/018 , B81B2203/058 , B81B2207/015 , B81C1/00214 , H01H2001/0068 , H01H2059/0054
摘要： A semiconductor torsional micro-electromechanical (MEM) switch is described having a conductive movable control electrode; an insulated semiconductor torsion beam attached to the movable control electrode, the insulated torsion beam and the movable control electrode being parallel to each other; and a movable contact attached to the insulated torsion beam, wherein the combination of the insulated torsion beam and the control electrode is perpendicular to the movable contact. The torsional MEM switch is characterized by having its control electrodes substantially perpendicular to the switching electrodes. The MEM switch may also include multiple controls to activate the device to form a single-pole, single-throw switch or a multiple-pole, multiple-throw switch. The method of fabricating the torsional MEM switch is fully compatible with the CMOS manufacturing process.
摘要翻译：描述了具有导电可移动控制电极的半导体扭转微机电（MEM）开关; 连接到可移动控制电极的绝缘半导体扭转梁，绝缘扭转梁和可移动控制电极彼此平行; 以及连接到所述绝缘扭力梁的可动触头，其中所述绝缘扭转梁和所述控制电极的组合垂直于所述可动触头。扭转MEM开关的特征在于其控制电极基本上垂直于开关电极。 MEM开关还可以包括多个控制以激活该装置以形成单极单掷开关或多极多掷开关。制造扭转MEM开关的方法与CMOS制造工艺完全兼容。

7. 发明授权

US07355271B2 Flexible assembly of stacked chips 有权
标题翻译：堆叠芯片的灵活组装
公开(公告)号：US07355271B2
公开(公告)日：2008-04-08
申请号：US10573561
申请日：2003-09-30
申请人： Richard P. Volant , Kevin S. Petrarca , George F. Walker
发明人： Richard P. Volant , Kevin S. Petrarca , George F. Walker
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2221/68372 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/18 , H01L2224/24137 , H01L2224/48091 , H01L2224/48227 , H01L2224/49431 , H01L2224/49433 , H01L2224/73209 , H01L2224/73259 , H01L2224/73267 , H01L2224/82005 , H01L2224/9222 , H01L2225/06524 , H01L2225/06527 , H01L2225/06579 , H01L2225/06589 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.
摘要翻译：描述了由多个折叠集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片的电连接的互连路径，并且至少一个芯片（130）是提供与衬底（500），封装或印刷电路板的附加互连布线。进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

8. 发明授权

US06924185B2 Fuse structure and method to form the same 失效
标题翻译：保险丝结构和方法形成相同
公开(公告)号：US06924185B2
公开(公告)日：2005-08-02
申请号：US10680618
申请日：2003-10-07
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
摘要翻译：用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。保险丝元件是电镀，无电镀，或是超薄保险丝。

9. 发明授权

US06339024B1 Reinforced integrated circuits 失效
标题翻译：强化集成电路
公开(公告)号：US06339024B1
公开(公告)日：2002-01-15
申请号：US09605728
申请日：2000-06-28
申请人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
发明人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
IPC分类号： H01L2044
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.
摘要翻译：一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。

10. 发明授权

US06927472B2 Fuse structure and method to form the same 失效
公开(公告)号：US06927472B2
公开(公告)日：2005-08-09
申请号：US09992344
申请日：2001-11-14
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

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