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    • 2. 发明授权
    • Memory error detecting apparatus and method
    • 存储器错误检测装置和方法
    • US08738976B2
    • 2014-05-27
    • US13163606
    • 2011-06-17
    • Rikizo NakanoOsamu IshibashiSadao Miyazaki
    • Rikizo NakanoOsamu IshibashiSadao Miyazaki
    • G11C29/00
    • G11C29/44G11C5/00G11C5/04G11C29/56G11C2029/4002
    • A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.
    • 一种用于检测对象存储器的错误的存储器错误检测装置,所述存储器错误检测装置包括连接到所述对象存储器的存储器总线,连接到所述存储器总线的镜像存储器,以便接收与要写入的数据相同的数据 从所述主体存储器读取所接收的数据被写入所述镜像存储器,地址获取部分,被配置为获取与写入所述对象存储器的数据相关的地址;镜像存储器控制器,被配置为控制数据写入或读取; 基于所获取的地址的镜像存储器,比较器,被配置为比较从所述对象存储器读取的数据和从所述镜像存储器读取的数据;以及错误检测器,被配置为基于所述比较的结果来检测数据错误。
    • 3. 发明授权
    • Memory controlling apparatus and method
    • 存储器控制装置及方法
    • US08495463B2
    • 2013-07-23
    • US12725893
    • 2010-03-17
    • Sadao MiyazakiOsamu IshibashiRikizo Nakano
    • Sadao MiyazakiOsamu IshibashiRikizo Nakano
    • G11C29/00
    • G11C29/44G11C5/04G11C29/4401G11C29/76G11C2029/0407G11C2029/1208
    • A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.
    • 提供存储器控制装置。 存储器控制装置被配置为控制对包括多个存储区域的存储装置的访问。 存储器控制装置包括:缺陷检测单元,被配置为检测可能不存储数据的存储区域的缺陷区域。 存储器控制装置还包括:存储处理单元,被配置为将包括使用缺陷检测单元检测到的缺陷区域的地址信息的缺陷信息存储到存储区域中。 数据写入单元也包括在存储器控制装置中。 数据写入单元被配置为基于使用存储处理单元存储的缺陷信息将已写入缺陷区域的数据写入除了包括缺陷区域的存储区域之外的存储区域中。
    • 6. 发明授权
    • Data processing apparatus
    • 数据处理装置
    • US08135971B2
    • 2012-03-13
    • US12495991
    • 2009-07-01
    • Sadao MiyazakiOsamu IshibashiRikizo NakanoYoshinori Mesaki
    • Sadao MiyazakiOsamu IshibashiRikizo NakanoYoshinori Mesaki
    • G06F1/00
    • G06F12/0802G06F2212/2024G06F2212/222Y02D10/13
    • A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.
    • 数据处理装置包括:CPU,包括寄存器,高速缓冲存储器,配置为与高速缓存存储器交换数据的主存储器;被配置为控制主存储器和高速缓冲存储器之间的数据交换的控制部分,以及电源 配置为向寄存器,高速缓冲存储器和主存储器供电的部件。 寄存器,高速缓冲存储器和主存储器都被配置为在不从电源部分提供电力的情况下存储数据并将其保存在其中。 控制部被配置为停止CPU访问在电源部中发生异常的寄存器,高速缓冲存储器和主存储器。