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    • 7. 发明授权
    • Automatic logic designing method and system
    • 自动逻辑设计方法和系统
    • US5504690A
    • 1996-04-02
    • US108044
    • 1993-08-16
    • Naohiro KageyamaToru ShonaiRikako SuzukiTakashi OkadaKazuhiko IijimaHiroyuki NakajimaChihei MiuraTsuguo Shimizu
    • Naohiro KageyamaToru ShonaiRikako SuzukiTakashi OkadaKazuhiko IijimaHiroyuki NakajimaChihei MiuraTsuguo Shimizu
    • G06F17/50
    • G06F17/5045
    • An automatic logic designing method and system in which a control table describing a condition and a behavior corresponding to the condition which express the specification of a computer is inputted and processed in a processor so that a logic circuit having no redundancy which can be easily seen by the designer is designed at a high speed. The control table is converted into the logic circuit whose function is expressed by a detailed Boolean expression. In an instance, selector logics are allocated in consideration of the polarity of the logic. A redundancy detection process or a redundancy logic elimination process is executed for the redundancy logics designated by a redundancy indicate file. A signal name which can be easily understood by the logic designer is formed. An implementing system includes an input control table file, a functional structure converting section of a conditional equation and a behavioral structure, a regular logic expanding processing section, and a redundancy logic elimination processing section, so that the logic circuit formed is outputted to a Boolean expression file.
    • 一种自动逻辑设计方法和系统,其中描述与表达计算机的规格的条件相对应的条件和行为的控制表在处理器中被输入和处理,使得不具有冗余的逻辑电路可以容易地被 设计师是高速设计的。 控制表转换为逻辑电路,其功能由详细的布尔表达式表示。 在一种情况下,考虑到逻辑的极性来分配选择器逻辑。 对由冗余指示文件指定的冗余逻辑执行冗余检测处理或冗余逻辑消除处理。 可以形成由逻辑设计者容易理解的信号名称。 实现系统包括输入控制表文件,条件方程式的功能结构转换部分和行为结构,规则逻辑扩展处理部分和冗余逻辑消除处理部分,使得形成的逻辑电路输出到布尔值 表达文件。