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1. 外观设计

USD704645S1 Housing for a connector 有权
公开(公告)号：USD704645S1
公开(公告)日：2014-05-13
申请号：US29417811
申请日：2012-04-09
申请人： Rika Nomura , Koji Nakagawa , Norio Chujo , Yuichi Koreeda
设计人： Rika Nomura , Koji Nakagawa , Norio Chujo , Yuichi Koreeda

2. 外观设计

USD705172S1 Housing for a connector 有权
标题翻译：连接器外壳
公开(公告)号：USD705172S1
公开(公告)日：2014-05-20
申请号：US29417799
申请日：2012-04-09
申请人： Rika Nomura , Koji Nakagawa , Norio Chujo , Yuichi Koreeda
设计人： Rika Nomura , Koji Nakagawa , Norio Chujo , Yuichi Koreeda

3. 发明授权

US09698783B2 Driver integrated circuit 有权
公开(公告)号：US09698783B2
公开(公告)日：2017-07-04
申请号：US14122623
申请日：2012-05-24
申请人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
发明人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
IPC分类号： H03K19/0175 , H03F1/52 , H03F3/195 , H03F3/21 , H03F3/30
CPC分类号： H03K19/0175 , H01L2224/48137 , H01L2924/181 , H03F1/52 , H03F3/195 , H03F3/211 , H03F3/3022 , H03F2200/189 , H03K19/017509 , H01L2924/00012
摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).

4. 发明授权

US08451063B2 Wideband low noise sensor amplifier circuit 有权
标题翻译：宽带低噪声传感器放大电路
公开(公告)号：US08451063B2
公开(公告)日：2013-05-28
申请号：US12892988
申请日：2010-09-29
申请人： Masayoshi Takahashi , Norio Chujo , Masami Makuuchi
发明人： Masayoshi Takahashi , Norio Chujo , Masami Makuuchi
IPC分类号： H03F3/08
CPC分类号： H03F1/08 , H03F3/45098 , H03F2200/213 , H03F2200/261 , H03F2200/411 , H03F2203/45458
摘要： A circuit having a sensor with a stray capacitance value. An output from the sensor is connected to the input of an amplifier while a negative capacitance circuit is electrically connected in parallel with the sensor output. The negative capacitance circuit reduces the effect of the sensor stray capacitance to provide an increased bandwidth and decreased noise on the amplifier output.
摘要翻译：具有具有杂散电容值的传感器的电路。传感器的输出连接到放大器的输入端，而负电容电路与传感器输出端并联电连接。负电容电路降低了传感器杂散电容的影响，从而提高了放大器输出端的带宽和降低的噪声。

5. 发明申请

US20120128292A1 Photoelectric Composite Wiring Module and Method for Manufacturing Same 有权
标题翻译：光电复合布线模块及其制造方法
公开(公告)号：US20120128292A1
公开(公告)日：2012-05-24
申请号：US13382459
申请日：2010-06-02
申请人： Saori Hamamura , Naoki Matsushima , Madoka Minagawa , Satoshi Kaneko , Norio Chujo , Yasunobu Matsuoka , Toshiki Sugawara , Tsutomu Kono
发明人： Saori Hamamura , Naoki Matsushima , Madoka Minagawa , Satoshi Kaneko , Norio Chujo , Yasunobu Matsuoka , Toshiki Sugawara , Tsutomu Kono
IPC分类号： G02B6/12 , H01L33/48
CPC分类号： G02B6/4201 , G02B6/424 , G02B6/4244 , G02B6/4246 , G02B6/4257 , G02B6/428 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/3512 , Y10T29/49146
摘要： A photoelectric composite wiring module, being superior in performances and mass-productivity thereof, and a transmission apparatus of applying that therein are provided.Optical devices 2a and 2b are disposed on a circuit board 1, so that they are optically coupled with optical guides 11 formed on the circuit board 1, wherein a filet-like resin is formed on a side surface of a bump, which is formed on side surfaces or/and upper portions of the optical devices, on an upper layer thereof being compressed a resin film to be adhered thereon, thereby forming an insulation film 31, and an electric wiring layer 3 is laminated, so that the electrodes of the optical devices 2 and wirings of the electric wiring layer are electrically connected with, and further thereon is mounted a semiconductor element 4; thereby obtaining the structure for brining the transmission speed to be high per channel, and for preventing the power consumption from increasing. Also, it has the structure of not causing deterioration of the optical devices due to ill influences of moisture, thereby achieving high reliability. Further, it also produces an easy connecting method with a transmission apparatus, and high productivity thereof.
摘要翻译：提供了一种性能优良，批量生产率高的光电复合布线模块以及其中应用的发送装置。光学器件2a和2b设置在电路板1上，使得它们与形成在电路板1上的光导11光学耦合，其中在凸起的侧表面上形成file状树脂，其形成在光学元件的侧表面或/或上部在其上层被压缩以粘附在其上的树脂膜，从而形成绝缘膜31，并且层叠电布线层3，使得光学器件的电极器件2和布线层的布线电连接，并且其上安装有半导体元件4; 从而获得用于使传输速度提高到每个通道高的结构，并且用于防止功耗增加。此外，其具有不会由于湿气的不良影响而导致光学元件劣化的结构，从而实现高可靠性。此外，它还产生与传动装置的简单连接方法，并且其生产率高。

6. 发明授权

US07965765B2 Adjustment method, circuit, receiver circuit and transmission equipment of waveform equalization coefficient 有权
标题翻译：调整方法，电路，接收机电路和传输设备的波形均衡系数
公开(公告)号：US07965765B2
公开(公告)日：2011-06-21
申请号：US11965783
申请日：2007-12-28
申请人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
发明人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.
摘要翻译：在波形均衡系数的调整方法中，仅在任意信号序列的情况下测量抖动和幅度之一并且调整波形均衡系数。特别地，使用除010信号或101信号之外的接收信号的信号，测量码反转时间。由于在使用这种信号的情况下的代码反转时间与传统技术相比变得更陡峭，所以可以减小波形均衡系数的调整时间。

7. 发明申请

US20110026878A1 Optical I/O Array Module and Its Fabrication Method 有权
标题翻译：光学I / O阵列模块及其制作方法
公开(公告)号：US20110026878A1
公开(公告)日：2011-02-03
申请号：US12844452
申请日：2010-07-27
申请人： Yasunobu MATSUOKA , Toshiki Sugawara , Koichiro Adachi , Naoki Matsushima , Saori Hamamura , Madoka Minagawa , Norio Chujo
发明人： Yasunobu MATSUOKA , Toshiki Sugawara , Koichiro Adachi , Naoki Matsushima , Saori Hamamura , Madoka Minagawa , Norio Chujo
IPC分类号： G02B6/12 , G02B6/30 , H01R43/00
CPC分类号： G02B6/43 , G02B6/4214 , G02B6/423 , H01S5/423 , Y10T29/49117
摘要： In fabricating an optical I/O array module, an optical waveguide provided with mirror parts, each having a tapered face, is formed on a substrate, a convex shaped member or a concave shaped member is placed at spots above the respective mirror parts of the optical waveguide, and laser diode arrays and photo diode arrays, provided with either a concave shape, or a convex shape, are mated with, or into the convex shaped member or the concave shaped member before being mounted. Further, there are formed multiple filmy layers, on which an LSI where a driver IC LSI of optical elements, and an amplifier LSI of the optical elements are integrated.
摘要翻译：在制造光学I / O阵列模块时，在衬底上形成具有锥面的镜部分的光波导，凸形或凹形的部件位于光波导，激光二极管阵列和具有凹形或凸形的光电二极管阵列在安装之前与凸形构件或凹形构件配合或配合。此外，形成有多个膜层，其上集成有光学元件的驱动器IC LSI和光学元件的放大器LSI的LSI。

8. 发明授权

US08406581B2 Photoelectric composite wiring module and method for manufacturing same 有权
标题翻译：光电复合布线模块及其制造方法
公开(公告)号：US08406581B2
公开(公告)日：2013-03-26
申请号：US13382459
申请日：2010-06-02
申请人： Saori Hamamura , Naoki Matsushima , Madoka Minagawa , Satoshi Kaneko , Norio Chujo , Yasunobu Matsuoka , Toshiki Sugawara , Tsutomu Kono
发明人： Saori Hamamura , Naoki Matsushima , Madoka Minagawa , Satoshi Kaneko , Norio Chujo , Yasunobu Matsuoka , Toshiki Sugawara , Tsutomu Kono
IPC分类号： G02B6/12
CPC分类号： G02B6/4201 , G02B6/424 , G02B6/4244 , G02B6/4246 , G02B6/4257 , G02B6/428 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/3512 , Y10T29/49146
摘要： A photoelectric composite wiring module, being superior in performances and mass-productivity thereof, and a transmission apparatus of applying that therein are provided.Optical devices 2a and 2b are disposed on a circuit board 1, so that they are optically coupled with optical guides 11 formed on the circuit board 1, wherein a filet-like resin is formed on a side surface of a bump, which is formed on side surfaces or/and upper portions of the optical devices, on an upper layer thereof being compressed a resin film to be adhered thereon, thereby forming an insulation film 31, and an electric wiring layer 3 is laminated, so that the electrodes of the optical devices 2 and wirings of the electric wiring layer are electrically connected with, and further thereon is mounted a semiconductor element 4; thereby obtaining the structure for brining the transmission speed to be high per channel, and for preventing the power consumption from increasing. Also, it has the structure of not causing deterioration of the optical devices due to ill influences of moisture, thereby achieving high reliability. Further, it also produces an easy connecting method with a transmission apparatus, and high productivity thereof.
摘要翻译：提供了一种性能优良，批量生产率高的光电复合布线模块以及其中应用的发送装置。光学器件2a和2b设置在电路板1上，使得它们与形成在电路板1上的光导11光学耦合，其中在凸起的侧表面上形成file状树脂，其形成在光学元件的侧表面或/或上部在其上层被压缩以粘附在其上的树脂膜，从而形成绝缘膜31，并且层叠电布线层3，使得光学器件的电极器件2和布线层的布线电连接，并且其上安装有半导体元件4; 从而获得用于使传输速度提高到每个通道高的结构，并且用于防止功耗增加。此外，其具有不会由于湿气的不良影响而导致光学元件劣化的结构，从而实现高可靠性。此外，它还产生与传动装置的简单连接方法，并且其生产率高。

9. 发明授权

US08324925B2 Output buffer circuit and differential output buffer circuit, and transmission method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及其传输方式
公开(公告)号：US08324925B2
公开(公告)日：2012-12-04
申请号：US13106926
申请日：2011-05-13
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译：输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

10. 发明申请

US20090179666A1 OUTPUT BUFFER CIRCUIT, DIFFERENTIAL OUTPUT BUFFER CIRCUIT, OUTPUT BUFFER CIRCUIT HAVING REGULATION CIRCUIT AND REGULATION FUNCTION, AND TRANSMISSION METHOD 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US20090179666A1
公开(公告)日：2009-07-16
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。

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